ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet - Page 28

• Manufacturer Part Number: ADC1415S125/DB,598
• Description: BOARD DEMO FOR ADC1415S125
• Manufacturer: NXP Semiconductors
• Type: A/Dr

Specifications of ADC1415S125/DB,598

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 840mW @ 125Msps
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1415S125
• Product: Data Conversion Development Tools
• Conversion Rate: 125 MSPS
• Resolution: 14 bit
• Interface Type: SMA
• For Use With/related Products: ADC1415S125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5094

NXP Semiconductors
ADC1415S_SER
Product data sheet
11.5.7 Output codes versus input voltage
11.6.1 Register description
11.6 Serial Peripheral Interface (SPI)
Table 15.
The ADC1415S serial interface is a synchronous serial communications port that allows
easy interfacing with many commonly-used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin)
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is
transmitted (two instruction bytes and at least one data byte). The number of data bytes is
determined by the value of bits W1 and W2 (see
Table 16.
[1]
[2]
V
< −1
−1
−0.9998779
−0.9997559
−0.9996338
−0.9995117
....
−0.0002441
−0.0001221
0
+0.0001221
+0.0002441
....
+0.9995117
+0.9996338
+0.9997559
+0.9998779
+1
> +1
Bit
Description
INP
Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see
− V
INM
Output codes
Instruction bytes for the SPI
Offset binary
00 0000 0000 0000
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
00 0000 0000 0011
00 0000 0000 0100
....
01 1111 1111 1110
01 1111 1111 1111
10 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0010
....
11 1111 1111 1011
11 1111 1111 1100
11 1111 1111 1101
11 1111 1111 1110
11 1111 1111 1111
11 1111 1111 1111
All information provided in this document is subject to legal disclaimers.
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
MSB
7
A7
R/W
Rev. 4 — 17 December 2010
[1]
6
W1
A6
[2]
5
W0
A5
[2]
4
A12
A4
Table
Two’s complement
10 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0010
10 0000 0000 0011
10 0000 0000 0100
....
11 1111 1111 1110
11 1111 1111 1111
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
....
01 1111 1111 1011
01 1111 1111 1100
01 1111 1111 1101
01 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
ADC1415S series
3
A11
A3
17).
2
A10
A2
© NXP B.V. 2010. All rights reserved.
1
A9
A1
OTR pin
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table
LSB
0
A8
A0
28 of 42
17).