TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 38
TMP86C993XB
Manufacturer Part Number
TMP86C993XB
Description
EMULATION CHIP FOR TMP86F SSOP
Manufacturer
Toshiba
Datasheet
1.TMP86C993XB.pdf
(246 pages)
Specifications of TMP86C993XB
Accessory Type
Adapter
For Use With/related Products
TMP86F SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2.2
System Clock Controller
2.2.4.3
timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes.
IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
Note:Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals.
1. Timing generator stops feeding clock to peripherals except TBT.
2. The data memory, CPU registers, program status word and port output latches are all held in the
3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and
status in effect before IDLE0 and SLEEP0 modes were entered.
SLEEP0 modes.
(Normal release mode)
Figure 2-12 IDLE0 and SLEEP0 Modes
No
No
No
No
CPU and WDT are halted
Execution of the instruction
Page 24
which follows the IDLE0,
Starting IDLE0, SLEEP0
Stopping peripherals
Interrupt processing
SLEEP0 modes start
modes by instruction
TBTCR<TBTEN>
by instruction
TBT interrupt
source clock
Reset input
IMF = "1"
instruction
enable
falling
= "1"
edge
TBT
Yes
Yes
No
Yes
Yes (Interrupt release mode)
Yes
Reset
TMP86FH92DMG
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