TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 100

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3
Function
Example 1 :Generating an interrupt 1 ms after the rising edge of the input pulse to the TC1 pin
Example 2 :Generating an interrupt when the low-level pulse with 4 ms or more width is input to the TC1 pin
10.3.2
and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising or
falling edge is defined in TC1CR<TC1S>.
of 12/fc [s] or more is required to ensure edge detection. The rejection circuit is turned off in the SLOW1/2 or
SLEEP1/2 mode, but a pulse width of one machine cycle or more is required.
(fc = 16 MHz)
(fc = 16 MHz)
In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin,
Since the TC1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. A pulse width
External Trigger Timer Mode
・ When TC1CR<METT1> is set to “1” (trigger start and stop)
・ When TC1CR<METT1> is set to “0” (trigger start)
up-counter is cleared and halted and an INTTC1 interrupt request is generated.
the TC1DRA, the up-counter is cleared and halted without generating an interrupt request. Therefore,
this mode can be used to detect exceeding the specified pulse by interrupt.
up-counter is cleared and halted and an INTTC1 interrupt request is generated.
is ignored if detecting it before detecting a match between the up-counter and the TC1DRA.
When a match between the up-counter and the TC1DRA value is detected after the timer starts, the
If the edge opposite to trigger edge is detected before detecting a match between the up-counter and
After being halted, the up-counter restarts counting when the trigger edge is detected.
When a match between the up-counter and the TC1DRA value is detected after the timer starts, the
The edge opposite to the trigger edge has no effect in count up. The trigger edge for the next counting
LDW
DI
SET
EI
LD
LD
LDW
DI
SET
EI
LD
LD
(TC1DRA), 007DH
(EIRH). 3
(TC1CR), 00000100B
(TC1CR), 00100100B
(TC1DRA), 01F4H
(EIRH). 3
(TC1CR), 00000100B
(TC1CR), 01110100B
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; 1ms ÷ 2
; IMF= “0”
; Enables INTTC1 interrupt
; IMF= “1”
; Selects the source clock and mode
; Starts TC1 external trigger, METT1= 0
; 4 ms ÷ 2
; IMF= “0”
; Enables INTTC1 interrupt
; IMF= “1”
; Selects the source clock and mode
; Starts TC1 external trigger, METT1= 1
7
7
/fc = 7DH
/fc = 1F4H
TMP86FH92DMG