TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 154

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3
SEI Operation
14.3
14.3.1
14.3.2
ously. The serial clock synchronizes the timing at which information on the two serial data lines are shifted or sampled.
Slave device can be selected individually using the slave select pin (SS pin). For unselected slave devices, data on the
SEI bus cannot be taken in.
During a SEI transfer, data transmission (serial shift-out) and reception (serial shift-in) are performed simultane-
When operating as the master devices, the SS pin can be used to indicate multiple-master bus connection.
SEI Operation
using two bits, CPHA and CPOL (SECR<CPHL,CPOL>).
fected).
same clock phase and polarity.
that of the slave device to which to transfer.
devices. Refer to Section “"14.5 SEI Transfer Formats "”.
The SEI clock allows its phase and polarity to be selected in software from four combinations available by
The clock polarity is set by CPOL to select between active-high or active-low (The transfer format is unaf-
The clock phase is set by CPHA. The master device and the slave devices to communicate with must have the
If multiple slave devices with different transfer formats exist on the same bus, the format can be changed to
The programmable data and clock timing of SEI allows connection to almost all synchronous serial peripheral
Controlling SEI clock polarity and phase
SEI data and clock timing
Table 14-2 Clock Phase and Polarity
CPHA
CPOL
SEI control register (SECR 002AH) bit 2
SEI control register (SECR 002AH) bit 3
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TMP86FH92DMG