TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 168

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.5
I
2
C Bus Control
15.5.4
15.5.5
15.5.6
15.5.7
ALS (Bit0 in I2CAR) to “0”, and set the SA (Bits7 to 1 in I2CAR) to the slave address.
ALS to “1”. With a free data format, the slave address and the direction bit are not recognized, and they are
processed as data from immediately after start condition.
be cleared to “0”.
receiver, the TRX should be cleared to “0”. When data with an addressing format is transferred in the slave mode,
the TRX is set to "1" by a hardware if the direction bit (R/W) sent from the master device is “1”, and is cleared
to “0” by a hardware if the bit is “0”. In the master mode, after an acknowledge signal is returned from the slave
device, the TRX is cleared to “0” by a hardware if a transmitted direction bit is “1”, and is set to "1" by a hardware
if it is “0”. When an acknowledge signal is not returned, the current condition is maintained.
"Table 15-2 TRX changing conditions in each mode" shows TRX changing conditions in each mode and TRX
value after changing
recognized. They are handled as data just after generating a start condition. The TRX is not changed by a hardware.
output on a bus after generating a start condition by writing “1” to the MST, TRX, BB and PIN. It is necessary
to set ACK to “1” beforehand.
When the serial bus interface circuit is used with an addressing format to recognize the slave address, clear the
When the serial bus interface circuit is used with a free data format not to recognize the slave address, set the
To set a master device, the MST (Bit7 in SBICRB) should be set to “1”. To set a slave device, the MST should
When a stop condition on the bus or an arbitration lost is detected, the MST is cleared to “0” by the hardware.
To set the device as a transmitter, the TRX (Bit6 in SBICRB) should be set to "1". To set the device as a
When a stop condition on the bus or an arbitration lost is detected, the TRX is cleared to “0” by the hardware.
When a serial bus interface circuit operates in the free data format, a slave address and a direction bit are not
When the BB (Bit5 in SBISRB) is “0”, a slave address and a direction bit which are set to the SBIDBR are
master device with the longest low-level period from among those master devices connected to the bus.
Slave address and address recognition mode specification
Master/slave selection
Transmitter/receiver selection
Start/stop condition generation
The clock pulse on the bus is determined by the master device with the shortest high-level period and the
Table 15-2 TRX changing conditions in each mode
Master
Mode
Slave
Mode
Mode
Direction Bit
"0"
"1"
"0"
"1"
A received slave address is the
same value set to I2CAR
ACK signal is returned
Page 154
Conditions
TRX after Changing
"0"
"1"
"1"
"0"
TMP86FH92DMG