MT18VDDT12872Y-265D2 Micron Technology Inc, MT18VDDT12872Y-265D2 Datasheet - Page 18
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT18VDDT12872Y-265D2
Manufacturer Part Number
MT18VDDT12872Y-265D2
Description
MODULE SDRAM DDR 1GB 184DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18VDDT12872Y-265D2.pdf
(39 pages)
Specifications of MT18VDDT12872Y-265D2
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
266MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
2.61A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 14: Capacitance
Note: 11; notes appear on pages 22–25
Table 15: Electrical Characteristics and Recommended AC Operating Conditions
DDR SDRAM Components Only
Notes: 1–5, 12–15, 29; notes appear on pages 22–25; 0°C
pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PARAMETER
Input/Output Capacitance: DQ, DQS
Input Capacitance: Command and Address, S#, CKE
Input Capacitance:CK, CK#
CL = 2.5
CL = 2
512MB, 1GB
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
256MB,
2GB
T
A
18
+70°C; V
SYMBOL
t
t
CK (2.5)
t
DQSCK
t
t
t
t
t
CK (2)
DQSQ
t
DQSH
DIPW
t
t
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQSL
DQSS
t
t
t
MRD
t
t
t
QHS
t
t
DSH
t
t
t
t
RAP
RCD
t
t
IPW
RAS
t
184-PIN DDR SDRAM RDIMM
DSS
t
t
t
RFC
DD
QH
DH
AC
CH
DS
HP
HZ
IH
IH
RC
CL
IS
IS
LZ
F
S
F
S
= V
SYMBOL
DD
Q = +2.5V ±0.2V
C
C
C
7.5/10
I0
I1
I2
-0.75
-0.75
-0.75
t
t
MIN
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
2.20
QHS
HP -
120
7.5
0.5
0.5
0.2
0.2
15
40
15
60
75
15
1
1
t
CH,
-262
t
120,000
CL
+0.75
+0.75
+0.75
MAX
0.55
0.55
1.25
0.75
0.5
13
13
©2004 Micron Technology, Inc. All rights reserved.
MIN
2.5
4
–
UNITS
t
t
t
t
t
t
t
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
3.5
5
4
NOTES
UNITS
40, 46
40, 46
22, 23
16, 37
16, 37
22, 23
26
26
23
23
30
12
12
12
12
31
44
pF
pF
pF