MT18VDDT12872Y-265D2 Micron Technology Inc, MT18VDDT12872Y-265D2 Datasheet - Page 12
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MT18VDDT12872Y-265D2
Manufacturer Part Number
MT18VDDT12872Y-265D2
Description
MODULE SDRAM DDR 1GB 184DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18VDDT12872Y-265D2.pdf
(39 pages)
Specifications of MT18VDDT12872Y-265D2
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
266MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
2.61A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Commands
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NOTE:
Table 9:
Used to mask write data; provided coincident with the corresponding data
pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (256MB), A0–A12 (512MB
3. BA0–BA1 provide device bank address; A0–A9, A11(256MB, 512MB) or A0–A9, A11, A12 (1GB, 2GB) provide column
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
NAME (FUNCTION)
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
WRITE Enable
WRITE Inhibit
Table 8, Commands Truth Table, and Table 9, DM
address.
address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge fea-
ture.
bursts with auto precharge enabled and for WRITE bursts.
BA1 are “Don’t Care.”
= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (256MB), A0–A12
(512MB
,
1GB), or A0–A13 (2GB) provide the op-code to be written to the selected mode register.
Commands Truth Table
DM Operation Truth Table
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
12
CS#
H
of commands and operations, refer to the 128Mb,
256Mb, 512MB, or 1Gb DDR SDRAM component data
sheet.
L
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS#
184-PIN DDR SDRAM RDIMM
X
H
H
H
H
L
L
L
L
,
CAS#
1GB), or A0–A13 (2GB) provide row
X
H
H
H
H
L
L
L
L
WE#
H
H
H
H
X
L
L
L
L
©2004 Micron Technology, Inc. All rights reserved.
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
DM
H
L
NOTES
6, 7
1
1
2
3
3
4
5
8
Valid
DQS
X