MT18VDDT12872Y-265D2 Micron Technology Inc, MT18VDDT12872Y-265D2 Datasheet - Page 16
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MT18VDDT12872Y-265D2
Manufacturer Part Number
MT18VDDT12872Y-265D2
Description
MODULE SDRAM DDR 1GB 184DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18VDDT12872Y-265D2.pdf
(39 pages)
Specifications of MT18VDDT12872Y-265D2
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
266MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
2.61A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
I
DDR SDRAM components only
Notes: 1–5, 8, 10, 12; notes appear on pages 22–25; 0°C
pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
(MIN);
clock cyle; Address and control inputs changing once every two clock
cycles
OPERATING CURRENT: One device bank; Active-Read Precharge; Burst
= 4;
I
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;
Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
MIN; CKE = HIGH; Address and other control inputs changing once per
clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode;
CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
t
cycle; Address and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
t
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;
t
cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge,
t
READ, or WRITE commands
DD
OUT
CK =
CK (MIN); I
CK =
CK =
t
= 0mA; Address and control inputs changing once per clock cycle
Specifications and Conditions – 1GB
RC =
t
t
t
CK (MIN); Address and control inputs change only during Active
CK (MIN); DQ, DM and DQS inputs changing twice per clock
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
CK =
t
RC (MIN);
OUT
t
IN
CK (MIN); DQ, DM and DQS inputs changing once per
= V
= 0mA
REF
t
t
t
CK =
CK =
CK =
t
for DQ, DQS, and DM
RC =
t
RC =
t
t
t
CK (MIN); CKE = (LOW)
CK (MIN);
CK (MIN);
t
RC (MIN);
t
RAS (MAX);
0.2V
t
t
REFC =
REFC = 7.8125µs
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
t
RFC (MIN)
T
A
t
RC =
t
16
CK =
+70°C; V
t
t
RC
CK =
t
CK
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
SYMBOL
= V
I
I
I
I
I
I
I
I
DD4W
I
I
DD3N
DD5A
I
I
DD2P
DD2F
DD3P
DD4R
DD
DD
DD1
DD6
DD7
DD
0
5
Q = +2.5V ±0.2V
2,340
2,880
2,970
2,790
5,220
7,200
-262
810
630
900
180
90
90
MAX
-26A/
-265/
2,070
2,610
2,610
2,430
5,040
6,300
©2004 Micron Technology, Inc. All rights reserved.
-202
720
540
810
180
90
90
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
21, 28,
21, 28,
20, 42
20, 42
20, 42
24, 44
24, 44
20, 43
44
45
44
41
20
9