MT16LSDF6464HG-133D2 Micron Technology Inc, MT16LSDF6464HG-133D2 Datasheet - Page 8

• Manufacturer Part Number: MT16LSDF6464HG-133D2
• Description: MODULE SDRAM 512MB 144SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDF6464HG-133D2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.096A
• Number Of Elements: 16
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in the Burst Definition
Table.
256MB Module
512MB Module
32/64 Meg x 64 SDRAM SODIMM
SD16C32_64x64HG_A.pm6; Rev. A, Pub 7/01
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
*Should program
M11 and M10 = “0, 0, 0”
to ensure compatibility
Mode Register Definition
with future devices.
*Should program
12
A12
Reserved*
Reserved* WB
11
11
A11
A11
10
10
A10
A10
WB
M9
0
1
9
9
A9
A9
Op Mode
Op Mode
8
8
A8
A8
Diagram
7
7
A7
A7
Programmed Burst Length
M8
0
Single Location Access
CAS Latency
CAS Latency
-
6
6
Write Burst Mode
A6
A6
5
5
M7
A5
A5
0
-
4
4
A4
A4
M3
BT
BT
Defined
0
1
M6-M0
3
3
A3
A3
-
M2
M6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
Burst Length
2
2
A2
A2
M1
M5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
1
0
1
0
1
0
1
0
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
A1
A1
0
0
A0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Mode Register (Mx)
Address Bus
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
8
NOTE: 1. For full-page accesses: y = 512.
Length
Burst
Page
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Full
(y)
2
4
8
2. For a burst length of two, A1-A8 select the block-
3. For a burst length of four, A2-A8 select the block-
4. For a burst length of eight, A3-A8 select the block-
5. For a full-page burst, the full row is selected and
6. Whenever a boundary of the block is reached
7. For a burst length of one, A0-A8 select the unique
of-two burst; A0 selects the starting column
within the block.
of-four burst; A0-A1 select the starting column
within the block.
of-eight burst; A0-A2 select the starting column
within the block.
A0-A8 select the starting column.
within a given sequence above, the following
access wraps within the block.
column to be accessed, and mode register bit M3
is ignored.
Starting Column
A2 A1 A0
(location 0-y)
0
0
0
0
1
1
1
1
n = A0-A8
Address
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
Burst Definition
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cn, Cn + 1, Cn + 2
Table
Type = Sequential
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
SDRAM SODIMM
256/512MB (x64)
Order of Accesses Within a Burst
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
PRELIMINARY
©2001, Micron Technology, Inc.
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0