MT16LSDF6464HG-133D2 Micron Technology Inc, MT16LSDF6464HG-133D2 Datasheet - Page 4

• Manufacturer Part Number: MT16LSDF6464HG-133D2
• Description: MODULE SDRAM 512MB 144SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDF6464HG-133D2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.096A
• Number Of Elements: 16
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN DESCRIPTIONS
32/64 Meg x 64 SDRAM SODIMM
SD16C32_64x64HG_A.pm6; Rev. A, Pub 7/01
RAS#, CAS#, WE#
DQMB0–DQMB7
CKE0, CKE1
DQ0–DQ63
SYMBOL
CK0, CK1
BA0, BA1
S0#, S1#
A0-A12
SDA
SCL
V
V
DD
SS
Supply
Output
Output
Supply
Input/
Input/
Input
Input
TYPE
Input
Input
Input
Input
Input
Input
Command Inputs RAS#, CAS#, and WE# (along with S0#) define
the command being entered.
signals are sampled on the positive edge of CK. CK also increments
the internal burst counter and controls the output registers.
Clock Enable: CKE0 and CKE1 activates (HIGH) and deactivates
(LOW) the CK0-CK1 signals. Deactivating the clock provides
POWER-DOWN and SELF REFRESH operation (all device banks idle)
or CLOCK SUSPEND operation (burst access in progress). CKE0 and
CKE1 are synchronous except after the device enters power-down
and self refresh modes, where CKE0 and CKE1 become asynchro-
nous until after exiting the same mode. The input buffers,
including CK0-CK1, are disabled during power-down and self
refresh modes, providing low standby power.
(registered HIGH) the command decoder. All commands are masked
when S0# and S1# are registered HIGH. S0# and S1# are considered
part of the command code.
Input Mask: DQMB is an input mask signal for write accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE cycle.
The output buffers are placed in a High-Z state (after a two-clock
latency) when DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which internal device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
BA0 is also used to program the twelfth bit of the Mode Register.
Address Inputs: A0-A12 are sampled during the ACTIVE
command (row-address A0-A12) and READ/WRITE command
(column-address A0-A9, A11 [x4]; A0-A9 [x8]; A0-A8 [x16]; with A10
defining auto precharge) to select one location out of the memory
array in the respective device bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH) or bank selected by (A10 LOW). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
presence-detect data transfer to and from the module.
Data I/Os: Data bus.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and data out of the presence-detect
portion of the module.
Power Supply: +3.3V ±0.3V.
Ground.
Clock: CK0 and CK1 are driven by the system clock. All SDRAM input
Chip Select: S0# and S1# enable (registered LOW) and disable
Serial Clock for Presence-Detect: SCL is used to synchronize the
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
SDRAM SODIMM
256/512MB (x64)
PRELIMINARY
©2001, Micron Technology, Inc.