MT9VDDF6472Y-335F1 Micron Technology Inc, MT9VDDF6472Y-335F1 Datasheet - Page 17

• Manufacturer Part Number: MT9VDDF6472Y-335F1
• Description: MODULE DDR SDRAM 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDF6472Y-335F1

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 167MHz
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.575A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1293; MT9VDDF6472Y-335F1

Table 14: Capacitance
Note: 11; notes appear on pages 20–23
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 8, 10, 12; notes appear on pages 20–23; 0°C
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
PARAMETER
Input/Output Capacitance: DQ, DQS, DM
Input Capacitance: Command and Address, S#, CKE
Input Capacitance: CK, CK#
Operating Conditions (-335, -262)
CL = 2.5
CL = 2
T
A
17
SYMBOL MIN
+70°C; V
t
t
t
t
DQSCK
t
t
t
t
CK (2.5)
t
CK (2)
DQSQ
DQSH
t
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
MRD
t
t
QHS
t
t
t
DSH
t
t
t
t
RAP
t
RCD
t
DSS
t
t
IPW
RAS
RFC
t
t
DH
QH
AC
CH
DS
HP
HZ
IH
IH
RC
CL
IS
IS
RP
LZ
F
S
F
S
256MB, 512MB (x72, ECC, SR)
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
-0.60
-0.70
t
t
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.75
0.75
0.80
0.80
2.20
-0.7
QHS
= V
HP -
7.5
0.2
0.2
12
15
60
72
15
15
42
6
t
DD
CH,
SYMBOL
-335
Q = +2.5V ±0.2V
120,000
C
C
C
t
MAX
+0.60
+0.70
CL
I0
I1
I2
+0.7
0.55
0.55
0.35
1.25
0.50
13
13
t
-0.75
7.5/10
-0.75
-0.75
t
MIN
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
2.20
QHS
HP -
7.5
0.5
0.5
0.2
0.2
15
42
15
60
75
15
15
1
1
t
CH,
©2004 Micron Technology, Inc. All rights reserved.
-262
MIN
2.5
120,000
4
–
MAX
+0.75
+0.75
+0.75
t
0.55
0.55
1.25
0.50
CL
0.5
13
13
MAX
3.5
5
4
UNITS NOTES
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
UNITS
40, 46
40, 46
23, 27
23, 27
22, 23
16, 37
16, 37
22, 23
31, 49
pF
pF
pF
26
26
12
12
44
27
30
12
12