MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 58

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
The APIO Setup register programs the resistor pullup
and the logic level for APIO1–APIO4.
AP<4:1>PU: APIO Resistor Pullup bits (default = 1111).
AP_PU controls the internal 500kΩ (typ) pullup resistor
on the corresponding APIO_. AP_PU = 0 disables the
pullup resistor and AP_PU = 1 connects the pullup
resistor to AV
the corresponding APIO_ is configured as an input.
AP<4:1>LL: APIO Logic-Level bits (default = 0000). If
APIO_ is programmed as a GPO, set the corresponding
AP_LL = 0 to set APIO_ to a logic-low level or set AP_LL
= 1 to set APIO_ to a logic-high level. A read from AP_LL
returns the logic level at the corresponding APIO_ when
the register is read, regardless of the APIO mode.
The Digital Programmable Input/Output (DPIO) Control
register programs the modes of the DPIO1–DPIO4.
DPIO1–DPIO4 are referenced to DV
Digital I/O in the Electrical Characteristics table).
DP_MD<3:0>: DPIO_ Mode Configuration bits (default
= 0000). DP_MD<3:0> configures the corresponding
DPIO_ (see Table 31).
The DPIO Setup register configures the pullup resistor
and logic level on DPIO1–DPIO4.
DP<4:1>PU: DPIO Resistor Pullup bits (default = 1111).
DP_PU controls the internal 500kΩ (typ) pullup resistor
on the corresponding DPIO_. DP_PU = 0 disables the
pullup resistor and DP_PU = 1 connects the pullup
resistor to DV
the corresponding DPIO_ is configured as an input.
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DD
DD
DP4MD3
DP2MD3
MSB
. The pullup resistor is active only when
. The pullup resistor is active only when
0
0
AP4PU
DP4PU
MSB
MSB
1
1
DP4MD2
DP2MD2
0
0
AP3PU
DP3PU
DPIO Control Register
1
1
APIO Setup Register
DPIO Setup Register
DD
and DGND (see
DP4MD1
DP2MD1
AP2PU
DP2PU
0
0
1
1
DP4MD0
DP2MD0
AP1PU
DP1PU
0
0
1
1
DP<4:1>LL: DPIO Logic-Level bits (default = 0000). If
DPIO_ is programmed as a GPO, set the correspond-
ing DP_LL = 0 to set DPIO_ to a logic-low level or set
DP_LL = 1 to set DPIO_ to a logic-high level. A read
from DP_LL returns the logic level at the corresponding
DPIO_ when the register is read, regardless of the
DPIO mode.
DP3MD3
DP1MD3
DP4LL
AP4LL
0
0
0
0
DP3MD2
DP1MD2
DP3LL
AP3LL
0
0
0
0
DP3MD1
DP1MD1
DP2LL
AP2LL
0
0
0
0
DP3MD0
DP1MD0
AP1LL
DP1LL
LSB
LSB
LSB
0
0
0
0