MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 49

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DAC Control register configures the power states for
DACA, DACB, the op amps, DAC reference buffer, and
the internal reference. The DAC Control register also
controls the DACA and DACB input and output register
write modes. At power-up, all DACs and op amps are
powered down. When powered down, the outputs of the
DAC buffers and op amps are high impedance.
DAPD<1:0>: DACA Power-Down bits (default = 00).
DAPD<1:0> control the power-down states and write
modes for DACA (see Table 14).
DBPD<1:0>: (MAX1329 only) DACB Power-Down bits
(default = 00). DBPD<1:0> control the power-down states
and write modes for a DACB write as shown in Table 15.
Table 14. DACA Power-Down Bit
Configuration
MAX1329
NAME
DEFAULT
MAX1330
NAME
DEFAULT
DAPD1
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
0
0
1
1
DAPD0
0
1
0
1
______________________________________________________________________________________
DAPD1
DAPD1
DACA POWER
Powered down
MSB
MSB
Powered up
Powered up
Powered up
0
0
MODE
DAPD0
DAPD0
DAC Control Register
0
0
Write input and output
Write input and output
DACA WRITE MODE
Shift input to output
Write input register
register
register
register
DBPD1
X
X
0
DBPD0
OA2E
0
0
OA1E: Op Amp 1 Enable bit (default = 0). Set OA1E = 1
to power up op amp 1.
OA2E (MAX1330 only): Op Amp 2 Enable bit (default =
0). Set OA2E = 1 to power up op amp 2.
DREF<1:0>: DAC Reference Buffer bits (default = 00).
DREF<1:0> sets the DAC reference buffer gain when
REFE = 0 (see Table 16). DREF<1:0> sets the REFDAC
voltage when the REFE = 1.
REFE: Internal Reference Enable bit (default = 0). REFE
= 1 enables the internal reference and sets REFADJ to
2.5V. REFE = 0 disables the internal reference so an
external reference can be applied at REFADJ, which
drives the inputs to the ADC and DAC reference
buffers. This bit is mirrored in the ADC Control register
so that writing either location updates both bits.
Table 15. DACB Power-Down Bit
Configuration (MAX1329 Only)
DBPD1
0
0
1
1
OA1E
OA1E
DBPD0
0
0
0
1
0
1
DACB POWER
Powered down
DREF1
DREF1
Powered up
Powered up
Powered up
0
0
MODE
DREF0
DREF0
0
0
Shift input to output
Write input register
Write input and
Write input and
output register
output register
DACB WRITE
register
MODE
REFE
REFE
LSB
LSB
0
0
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