MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 26

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
Upon a power-on reset, the charge pump is disabled.
Enable the charge pump through the CP/VM Control
register. When the charge pump is in its off state, AV
is isolated from DV
enabled. To bypass the charge pump and directly con-
nect DV
through the CP/VM Control register (see Tables 21 and
22). During the on mode, the charge pump boosts
DV
ed output voltage at AV
voltage selections are 3.0V, 4.0V, or 5.0V.
The charge-pump clock and ADC clock are synchro-
nized from the same master clock. The charge pump
uses a pulse-width-modulation (PWM) scheme to regu-
late the output voltage. The charge pump supports a
maximum load of 25mA of current to an external device
including what is required for internal circuitry.
Three power modes are available for the MAX1329/
MAX1330: shutdown, sleep, and normal operation. In shut-
down mode, all functional blocks are powered down except
the serial interface, data registers, and wake-up circuitry (if
enabled). Sleep mode is identical to shutdown mode
except the DV
active. Global sleep or shutdown mode is initiated through a
Figure 3. Clock-Divider Block Diagram
26
OSCE
DD
OSCILLATOR
SCLK
4.9152MHz
INTERNAL
(OFF, ON)
______________________________________________________________________________________
and regulates the voltage to generate the select-
DD
to AV
1
DD
DD
0
voltage monitors (if enabled) remain
(/32, /64, /128, /256)
, enable (close) the bypass switch
CHARGE-PUMP
CLOCK DIVIDER
(/1, /2, /4, /8)
ADC CLOCK
DD
DIVIDER
(OFF, /1, /2, /4)
CLOCK INPUT
OSCE = 0
unless the bypass switch is
DD
DIVIDER
CLOCK OUTPUT
(OFF, /1, /2, /4)
. The charge-pump output
OSCE = 1
DIVIDER
CHARGE PUMP
(OFF, 3V, 4V, 5V)
MUX
Power Modes
(ACQUIRE CLKS)
(ADC CONTROL)
(ADC SETUP)
CLKIO
ADC
DD
DPIO configured as SLP or SHDN inputs. In normal mode,
each analog and digital block can be powered up or shut
down individually through its respective control register.
The MAX1329/MAX1330 provide two programmable volt-
age supervisors, one for DV
DV
and 2.7V by default) that are both enabled after a power-
on reset. On initial power-up, RST1 is assigned the 1.8V
monitor output and RST2 is assigned the 2.7V monitor
output, both for DV
2.7V threshold, the VM1A bit or VM1B bit, respectively, in
the Status register is set. The VM1A and VM1B status
bits can also be mapped to the interrupt generator.
The default states of RST1 and RST2 are open-drain
outputs but can be programmed as push-pull Status
register interrupts through the CP/VM Control register.
The AV
mable thresholds. If AV
threshold, the VM2 bit is set in the Status register. The
VM2 status bit can also be mapped to the interrupt
generator.
The interrupt generator accepts inputs from other internal
circuits to provide an interrupt to an external microcontroller
(µC). The sources for generating an interrupt are program-
mable through the serial interface. Possible sources
include a rising or falling edge on the digital and analog
programmable inputs, ADC alarms, an ADC conversion
complete, an ADC FIFO full, an ADC accumulator full, and
the voltage-supervisor outputs. The interrupt causes RST1
and/or RST2 to assert when configured as an interrupt out-
put. The interrupt remains asserted until the Status register
is read. See the CP/VM Control register for programming
the RST1 and RST2 outputs as interrupts and the Interrupt
Mask register for programming the interrupt sources.
The MAX1329/MAX1330 feature an internal oscillator,
which operates at a fixed frequency of 3.6864MHz. When
enabled, the internal oscillator provides the master clock
source for the ADC and charge pump. To allow external
devices to use the internally generated clock, configure
CLKIO as an output through the Clock Control register.
The CLKIO output frequency is configurable for
0.9216MHz, 1.8432MHz, and 3.6864MHz. When the inter-
nal oscillator is enabled, and regardless of the CLKIO out-
put frequency, the ADC and charge-pump clock dividers
always receive a 3.6864MHz clock signal (see Figure 3).
After a power-on reset, CLKIO defaults to an output with
the divider set to 2 (resulting in 1.8432MHz).
DD
voltage supervisor has two thresholds (set to 1.8V
Internal Oscillator and Programmable
DD
voltage supervisor provides three program-
DD
. If DV
DD
falls below the programmed
DD
DD
Voltage Supervisors
Interrupt Generator
and one for AV
falls below the 1.8V or
Clock Dividers
DD
. The