MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 57

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Analog Programmable Input/Output (APIO) Control
register configures the modes of APIO1–APIO4.
APIO1–APIO4 I/O logic levels are referenced to AV
AGND (see Analog I/O in the Electrical Characteristics
table). APIO_ is configurable as a general-purpose input,
Table 29. SPDT2 Switch Control Configuration
Table 30. APIO_ Mode Bit Configuration
NAME
DEFAULT
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
SPDT21
Reference, Voltage Monitors, and Temp Sensor
AP_MD1
BIT
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
SPDT20
BIT
0
X
X
X
X
1
0
X
X
X
X
1
AP4MD1
AP_MD0
______________________________________________________________________________________
MSB
0
0
1
0
1
DPIO4
X
X
X
X
X
X
X
X
0
1
0
1
AP4MD0
MODE
WUL
GPO
APIO Control Register
GPI
SPI
0
DPIO3
0
X
X
1
X
X
0
X
X
1
X
X
Digital input. APIO_ logic level read from AP_LL register bit.
Digital input. A falling edge on APIO_ sets the OSCE bit to 1 enabling the oscillator.
Digital output. Set the APIO_ logic level by writing to the AP_LL register bit.
Digital input or output. The SPI mode functions differ for each APIO1–APIO4.
AP3MD1
• APIO1 digital input. DOUT outputs the APIO1 logic level when CS is high, and
• APIO2 digital output. APIO2 outputs the DIN logic level when CS is high and
• APIO3 digital output. APIO3 outputs the SCLK logic level when CS is high and
• APIO4 digital output. APIO4 inverts and then outputs the CS logic level.
APIO1 is a GPI, when CS is low. Set the resistor pullup configuration with the
AP1PU bit.
becomes a GPO with the level set by AP2LL bit when CS is low.
becomes a GPO with the level set by the AP3LL bit when CS is low.
0
DPIO2
DD
X
X
X
X
X
X
X
X
0
1
0
1
and
AP3MD0
DPIO1
0
X
X
X
X
X
X
X
X
active-low wake-up input, general-purpose output, or seri-
al-interface, level-shifted buffered I/O.
AP_MD<1:0>: APIO_ Mode Configuration bits (default
= 00). AP_MD<1:0> configures the APIO_ mode
according to Table 30.
0
1
0
1
AP2MD1
SNO2-TO-SCM2 STATE
DESCRIPTION
0
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Open
Open
AP2MD0
SPDT2 SWITCH STATE
0
SNC2-TO-SCM2 STATE
AP1MD1
0
Closed
Closed
Closed
Closed
Closed
Closed
Open
Open
Open
Open
Open
Open
AP1MD0
LSB
0
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