MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 53

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The CP/VM (Charge Pump/Voltage Monitor) Control
register configures the interrupt polarity, charge-pump
output voltage settings and power-down, supply volt-
age bypass switch state, and the voltage monitor set-
tings for DV
INTP: Interrupt Polarity bit (default = 0). INTP controls
the output polarity for RST1 and RST2 when configured
as interrupt outputs. INTP = 0 results in active-low oper-
ation and INTP = 1 selects active-high operation.
VM1<1:0>: Voltage Monitor 1 (VM1) Control bits
(default = 00). VM1 monitors the voltage on DV
VM1<1:0> bits control the threshold and output settings
of VM1 (see Table 21). RST1 and RST2 are open-drain
outputs when configured as voltage monitor outputs
and are push-pull when configured as interrupt outputs.
The VM1A status bit is set when DV
1.8V threshold and the VM1B status bit is set when
DV
Table 20. ADC Acquisition Clock Bit
Configuration
Table 21. Voltage Monitor 1 Control Bit Configuration
NAME
DEFAULT
ACQCK1
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
DD
VM11
0
0
1
1
0
0
1
1
drops below the 2.7V threshold.
DD
ACQCK0
and AV
VM10
0
1
0
1
MSB
INTP
0
1
0
1
______________________________________________________________________________________
0
DD
.
GAIN = 1, 2
ADC ACQUISITION CLOCKS
RST1 OUTPUT
16
VM11
2
4
8
1.8V monitor
1.8V monitor
CP/VM Control Register
0
Interrupt
Interrupt
DD
drops below the
GAIN = 4, 8
VM10
0
16
32
4
8
DD
. The
RST2 OUTPUT
2.7V monitor
2.7V monitor
VM2CP2
Interrupt
Interrupt
0
VM2CP<2:0>: Voltage Monitor 2 (VM2) and Charge-
Pump Control bits (default = 000). VM2CP<2:0> control
the charge pump, the bypass switch, and the AV
age monitor. The charge pump generates a regulated
AV
(VM2CP = 100), the bypass switch internally shorts
DV
sets the VM2 Status bit when AV
the threshold.
CPDIV<1:0>: Charge-Pump Clock Divider bits (default =
00). The CPDIV<1:0> bits set the divider value for the
input clock to the charge pump (see Table 23). If OSCE
= 1, the input to the charge-pump clock divider is the
3.6864MHz oscillator output. If OSCE = 0 and
CLKIO<1:0> ≠ 00, the output of the CLKIO input divider
is applied to the input of the charge-pump clock divider.
The charge pump is optimized to operate with a clock
rate between 39kHz and 78kHz. Set the CPDIV<1:0>
and CLKIO<1:0> bits to provide the optimal clock
frequency for the charge pump.
DD
DD
supply voltage from a DV
to AV
VM2CP1
0
DD
(1.8V MONITOR)
. VM2 monitors the voltage on AV
VM1A STATE
VM2CP0
On
On
Off
Off
0
DD
CPDIV1
input. When activated
0
(2.7V MONITOR)
DD
VM1B STATE
drops below
On
Off
On
Off
CPDIV0
LSB
DD
DD
0
volt-
and
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