LTC3830EGN Linear Technology, LTC3830EGN Datasheet - Page 11

• Manufacturer Part Number: LTC3830EGN
• Description: IC DC/DC CONTRLR STEP-DWN 16SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC3830EGN

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 3.3V, Adj
• Current - Output: 20A
• Frequency - Switching: 200kHz
• Voltage - Input: 3 ~ 8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

SYNC METHOD
APPLICATIO S I FOR ATIO
External Clock Synchronization
The LTC3830 SHDN pin doubles as an external clock input
for applications that require a synchronized clock. An
internal circuit forces the LTC3830 into external synchro-
nization mode if a negative transition at the SHDN pin is
detected. In this mode, every negative transition on the
SHDN pin resets the internal oscillator and pulls the ramp
signal low, this forces the LTC3830 internal oscillator to
lock to the external clock frequency. The LTC3830-1 does
not have this external synchronization function.
The LTC3830 internal oscillator can be externally synchro-
nized from 100kHz to 500kHz. Frequencies above 300kHz
can cause a decrease in the maximum obtainable duty
cycle as rise/fall time and propagation delay take up a
larger percentage of the switch cycle. Circuits using these
frequencies should be checked carefully in applications
where operation near dropout is important—like 3.3V to
TERMINATION
UNDER SYNC
TRADITIONAL
KEEPS RAMP
WITH EARLY
AMPLITUDE
CONSTANT
LTC3830
RAMP
RAMP AMPLITUDE
Figure 5. External Synchronization Operation
SHDN
FREE RUNNING
ADJUSTED
RAMP SIGNAL
200kHz
U
U
W
WITH EXT SYNC
RAMP SIGNAL
U
3830 F05
2.5V converters. The low period of this clock signal must
not be >100µs, or else the LTC3830 enters shutdown
mode.
Figure 5 describes the operation of the external synchro-
nization function. A negative transition at the SHDN pin
forces the internal ramp signal low to restart a new PWM
cycle. Notice that with the traditional sync method, the
ramp amplitude is lowered as the external clock frequency
goes higher. The effect of this decrease in ramp amplitude
increases the open-loop gain of the controller feedback
loop. As a result, the loop crossover frequency increases
and it may cause the feedback loop to be unstable if the
phase margin is insufficient.
To overcome this problem, the LTC3830 monitors the
peak voltage of the ramp signal and adjusts the oscillator
charging current to maintain a constant ramp peak.
LTC3830 (16-LEAD)
LTC3830 (8-LEAD)
CIRCUITRY
CIRCUITRY
INTERNAL
V
INTERNAL
CC
V
/PV
CC
CC2
Figure 6. 16-Lead Power Supplies
Figure 7. 8-Lead Power Supplies
PV
CC2
LTC3830/LTC3830-1
PV
PV
CC1
CC1
G1
G2
G1
G2
V
V
IN
IN
Q1
Q2
Q1
Q2
L
L
O
O
+
+
3830 F6
3830 F7
11
C
C
OUT
OUT
V
V
3830fa
OUT
OUT