MAX1544ETL+ Maxim Integrated Products, MAX1544ETL+ Datasheet - Page 23

• Manufacturer Part Number: MAX1544ETL+
• Description: IC QUICK-PWM DUAL-PHASE 40-TQFN
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX1544ETL+

• Applications: Controller, AMD Hammer
• Voltage - Input: 2 ~ 28 V
• Number Of Outputs: 1
• Voltage - Output: 0.68 ~ 1.55 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Output Voltage: 0.675 V to 1.55 V
• Output Current: 40 A
• Input Voltage: 4 V to 28 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4. Output Voltage VID DAC Codes (SUS = GND)
The output UVP function is similar to foldback current
limiting, but employs a timer rather than a variable current
limit. If the MAX1544 output voltage is under 70% of the
nominal value, the controller activates the shutdown
sequence and sets the fault latch.
Once the controller ramps down to the 0V DAC code
setting, it forces the DL_ low-side gate driver high and
pulls the DH_ high-side gate driver low. Toggle SHDN
or cycle the V
fault latch and reactivate the controller. UVP is ignored
during output voltage transitions and remains blanked
for an additional 24 clock cycles after the controller
reaches the final DAC code value.
UVP can be disabled through the no-fault test mode
(see the No-Fault Test Mode section).
The MAX1544 features a thermal-fault protection circuit.
When the junction temperature rises above +160°C, a
thermal sensor activates the fault latch and the soft-
shutdown sequence. Once the controller ramps down
to the 0V DAC code setting, it forces the DL_ low-side
gate driver high, and pulls the DH_ high-side gate
driver low. Toggle SHDN or cycle the V
below 1V to clear the fault latch and reactivate the con-
troller after the junction temperature cools by 15°C.
Thermal shutdown can be disabled through the
no-fault test mode (see the No-Fault Test Mode section).
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CC
______________________________________________________________________________________
power supply below 1V to clear the
AMD Hammer CPU Core Power Supplies
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Output Undervoltage Shutdown
Dual-Phase, Quick-PWM Controller for
D1
Thermal-Fault Protection
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CC
power supply
VOLTAGE
OUTPUT
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
(V)
The latched-fault protection features and overlap mode
can complicate the process of debugging prototype
breadboards since there are (at most) a few milliseconds
in which to determine what went wrong. Therefore, a no-
fault test mode is provided to disable the fault protection
(overvoltage protection, undervoltage protection, and
thermal shutdown) and overlap mode. Additionally, the
test mode clears the fault latch if it has been set. The no-
fault test mode is entered by forcing 12V to 15V on
SHDN.
The Quick-PWM controller requires an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook’s 95%-efficient 5V system sup-
ply. Keeping the bias supply external to the IC
improves efficiency and eliminates the cost associated
with the 5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the 5V bias supply
can be generated with an external linear regulator.
The 5V bias supply must provide V
and V
drawn is:
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DD
I
BIAS
(gate-drive power), so the maximum current
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
= I
CC
5V Bias Supply (V
Multiphase Quick-PWM
D2
+ f
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SW
(Q
D1
G(LOW)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
No-Fault Test Mode
D0
+ Q
CC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(PWM controller)
G(HIGH)
CC
VOLTAGE
Shutdown
OUTPUT
and V
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
(V)
)
DD
23
)