ISL6566ACRZ-T Intersil, ISL6566ACRZ-T Datasheet - Page 18

• Manufacturer Part Number: ISL6566ACRZ-T
• Description: IC CTRLR PWM 3PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6566ACRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Fault Monitoring and Protection
The ISL6566A actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 13
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft-start. PGOOD pulls low during shutdown and releases
high after a successful soft-start. PGOOD transitions low
when an undervoltage, overvoltage, or overcurrent condition
is detected or when the controller is disabled by a reset from
ENLL, POR, or one of the no-CPU VID codes. If after an
undervoltage or overvoltage event occurs the output returns
to within under and overvoltage limits, PGOOD will return
high.
Undervoltage Detection
The undervoltage threshold is set at 82% of the VID code.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above 85% of the VID code.
Overvoltage Protection
The ISL6566A constantly monitors the difference between the
VSEN and RGND voltages to detect if an overvoltage event
occurs. During soft-start, while the DAC is ramping up, the
overvoltage trip level is the higher of DAC plus 150mV or a
fixed voltage, V
running in AMD Hammer, or VRM10 modes, and 1.97V for
VRM9 mode. Upon successful soft-start, the overvoltage trip
level is only DAC plus 150mV. OVP releases 50mV below its
trip point if it was “DAC plus 150mV” that tripped it, and
releases 100mV below its trip point if it was the fixed voltage,
V
protect the microprocessor load when an overvoltage
condition occurs, until the output voltage falls back within set
limits.
At the inception of an overvoltage event, LGATE1 and
LGATE2 signals are commanded high, PWM3 is
commanded low, and the PGOOD signal is driven low. This
turns on the lower MOSFETs and pulls the output voltage
below a level that might cause damage to the load. The
LGATE outputs remain high and PWM3 remains low until
VDIFF falls to within the overvoltage limits explained above.
The ISL6566A will continue to protect the load in this fashion
as long as the overvoltage condition recurs.
Once an overvoltage condition ends the ISL6566A continues
normal operation and PGOOD returns high.
OVP
, that tripped it. Actions are taken by the ISL6566A to
OVP
. The fixed voltage, V
18
OVP
, is 1.67V when
ISL6566A
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6566A is designed to protect the load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10kΩ resistor tied from PHASE to
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
power supply cuts off. For complete protection, the low side
MOSFET should have a gate threshold well below the
maximum voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6566A is designed to detect this
and shut down the controller. This event is detected by
monitoring the voltage on the IREF pin, which is a local
version of V
If VSEN or RGND become opened, VDIFF falls, causing the
duty cycle to increase and the output voltage on IREF to
increase. If the voltage on IREF exceeds “VDIFF+1V”, the
controller will shut down. Once the voltage on IREF falls
below “VDIFF+1V”, the ISL6566A will restart at the
beginning of soft-start.
Overcurrent Protection
The ISL6566A detects overcurrent events by comparing the
droop voltage, V
shown in Figure 13. The droop voltage, set by the external
current sensing circuitry, is proportional to the output current
as shown in Equation 7. A constant 100µA flows through
R
voltage exceeds the OCSET voltage, the overcurrent
protection circuitry activates. Since the droop voltage is
proportional to the output current, the overcurrent trip level,
I
as shown in Equation 14.
Once the output current exceeds the overcurrent trip level,
V
the converter to begin overcurrent protection procedures. At
the beginning of overcurrent shutdown, the controller turns
off both upper and lower MOSFETs. The system remains in
this state for a period of 4096 switching cycles. If the
controller is still enabled at the end of this wait period, it will
attempt a soft-start (as shown in Figure 14). If the fault
remains, the trip-retry cycles will continue indefinitely until
either the controller is disabled or the fault is cleared. Note
that the energy delivered during trip-retry cycling is much
less than during full-load operation, so there is no thermal
hazard.
R
MAX
DROOP
OCSET
OCSET
, can be set by selecting the proper value for R
, creating the OCSET voltage. When the droop
=
will exceed V
I
--------------------------------------------------------- -
OUT
MAX
DROOP
sensed at the outputs of the inductors.
⋅
100µ R
R
COMP
⋅
OCSET
, to the OCSET voltage, V
S
⋅
DCR
, and a comparator will trigger
OCSET
July 27, 2005
OCSET
(EQ. 14)
FN9200.2
, as
,