SE97BTP,547 NXP Semiconductors, SE97BTP,547 Datasheet - Page 33

• Manufacturer Part Number: SE97BTP,547
• Description: IC TEMP SENSOR DIMM 8HWSON
• Manufacturer: NXP Semiconductors

Specifications of SE97BTP,547

• Package / Case: 8-WSON (Exposed Pad), 8-HWSON
• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Comparator, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -40°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Temperature Threshold: + 150 C
• Full Temp Accuracy: 2 C
• Digital Output - Bus Interface: I2C
• Digital Output - Number Of Bits: 11 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Description/function: Temperature Sensor
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5055-2

NXP Semiconductors
SE97B_1
Product data sheet
8.9 SMBUS — SMBus register (22h, 8-bit read/write)
Table 26.
Table 27.
Bit
Symbol
Default
Access
Bit
15:8
7
6
5
4
3
2
Bit
Symbol
Default
Access
Symbol
RFU
DisableTimeout Disable SMBus time-out.
RFU
EnableSDTO
EventSleep
State
IntrClear
Mode
FlagUpdate
Mode
SMBUS - SMBus Time-out register bit allocation
SMBus Time-out register bit description
Timeout
Disable
[1]
[2]
R/W
15
R
0
7
0
Rev. 01 — 27 January 2010
RFU
Description
reserved; always ‘0’
When either of the Critical Trip or Alarm Window lock bits is set, this bit
cannot be altered until unlocked.
reserved; always ‘0’
SMBus time-out during Shutdown (CONFIG[8]).
Remark: DisableTimeout bit must be a logic 0 to enable this feature.
When either Critical Trip or Alarm Window lock bits are set, this bit
cannot be altered until unlocked.
State of EVENT output when SHMD bit is set.
When either Critical Trip or Alarm Window lock bits are set, this bit
cannot be altered until unlocked.
Interrupt Flop Clearing Mode.
When either Critical Trip or Alarm Window lock bits are set, this bit
cannot be altered until unlocked.
Update AAW, BAW and ACT flags after each new temperature
conversion.
When either Critical Trip or Alarm Window lock bits are set, this bit
cannot be altered until unlocked.
14
R
0
R
6
0
0 — SMBus time-out is enabled (default)
1 — SMBus time-out is disabled
0 — disable SMBus time-out
1 — enable SMBus time-out (default)
0 — EVENT pin state is frozen
1 — EVENT pin is de-asserted, state based on Polarity bit (default)
0 — allow clearing interrupt flop while in comparator mode (default)
1 — disable clearing interrupt flow while in comparator mode
0 — update AAW, BAW and ACT flags continuously (default)
1 — update flags with new temperature conversion
DDR memory module temp sensor with integrated SPD
Enable
SDTO
R/W
13
R
0
5
1
Event
Sleep
State
R/W
12
R
0
4
1
RFU
IntrClear
Mode
R/W
11
R
0
3
0
Update
Mode
Flag
R/W
10
R
0
2
0
© NXP B.V. 2010. All rights reserved.
RFU
R
9
0
R
1
0
SE97B
Disable
ARA
R/W
33 of 53
R
8
0
0
1