L6740L STMicroelectronics, L6740L Datasheet - Page 38

• Manufacturer Part Number: L6740L
• Description: IC HYBRID CONTROLLERS 48TQFP
• Manufacturer: STMicroelectronics

Specifications of L6740L

• Applications: Hybrid Controllers
• Voltage - Supply: 9 V ~ 15 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Number Of Outputs: 2
• Output Current: 170 A
• Input Voltage: 13.2 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Hybrid Controller: compatible with PVI and SVI CPUs
• Dual Controller: 2 to 4 scalable phases for CPU CORE, 1 phase for NB
• Dual Over-current Protection: Average and per-phase
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System control loop compensation
9.1
38/44
Figure 17. Control loop bode diagram and fine tuning (not in scale)
To obtain the desired shape an R
implementation. A zero at ω
integrator minimizes the static error while placing the zero ω
C resonance assures a simple -20 dB/Dec. shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.
Compensation network can be simply designed placing ω
over frequency ω
1/10 th of the switching frequency F
Compensation network guidelines
The compensation network design assures to having system response according to the
cross-over frequency selected and to the output filter considered: it is anyway possible to
further fine-tune the compensation network modifying the bandwidth in order to get the best
response of the system as follow (See
Having the fastest compensation network gives not the confidence to satisfy the
requirements of the load: the inductor still limits the maximum dI/dt that the system can
afford. In fact, when a load transient is applied, the best that the controller can do is to
“saturate” the duty cycle to its maximum (d
dV/dt is then limited by the inductor charge / discharge time and by the output capacitance.
In particular, the most limiting transition corresponds to the load removal since the inductor
results being discharged only by V
appliance).
R
C
R
F
F
F
[dB]
K
=
=
–
–
–
R
--------------------------------- -
------------------- -
dB
C
FB
R
O
F
Increase R
Decrease R
Increase C
system phase margin.
⋅
V
⋅
ω
ΔV
IN
L
LC
OSC
=
G
ω
F
LOOP
ω
T
ESR
⋅
as desired obtaining (always considering that ω
----- - ω
10
(s)
9
F
F
F
⋅
to increase the system bandwidth accordingly;
to move ω
to decrease the system bandwidth accordingly;
T
⋅
------------------------------------------ -
N
F
⋅
= 1/R
(
Z
R
F
F
LL
(s)
F
L
to low frequencies increasing as a consequence the
-C
OUT
F
+
SW
C
ESR
F
ω
F
T
series network is considered for the Z
):
(while it is charged by d
Figure
is then introduced together with an integrator. This
)
MAX
R
ω
F
17):
) or minimum (0) value. The output voltage
[dB]
K
dB
ω
LC
C
F
=
F
= ω
G
ω
F
F
LOOP
ω
in correspondence with the L-
ESR
MAX
LC
(s)
and imposing the cross-
T
V
might be not higher than
IN
-V
OUT
R
during a load
F
F
(s)
Z
ω
F
(s)
T
L6740L
ω