L6740L STMicroelectronics, L6740L Datasheet - Page 16

• Manufacturer Part Number: L6740L
• Description: IC HYBRID CONTROLLERS 48TQFP
• Manufacturer: STMicroelectronics

Specifications of L6740L

• Applications: Hybrid Controllers
• Voltage - Supply: 9 V ~ 15 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Number Of Outputs: 2
• Output Current: 170 A
• Input Voltage: 13.2 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Hybrid Controller: compatible with PVI and SVI CPUs
• Dual Controller: 2 to 4 scalable phases for CPU CORE, 1 phase for NB
• Dual Over-current Protection: Average and per-phase
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Hybrid CPU support and CPU_TYPE detection
5
Caution:
5.1
5.2
16/44
Hybrid CPU support and CPU_TYPE detection
L6740L is able to detect the type of the CPU-core connected and to configure itself
accordingly. At system start-up, on the rising-edge of the EN signal, the device monitors the
status of VID1 and configures the PVI mode (VID1 = 1) or SVI mode (VID1 = 0).
When in PVI mode, L6740L uses the information available on the VID[0: 5] bus to address
the CORE section output voltage according to
When in SVI mode, L6740L ignores the information available on VID0, VID4 and VID5 and
uses VID2 and VID3 as a SVI bus addressing the CORE and NB sections according to the
SVI protocol.
To avoid any risk of errors in CPU type detection (i.e. detecting SVI CPU when PVI CPU is
installed on the socket and vice versa), it is recommended to carefully control the start-up
sequencing of the system hosting L6740L in order to ensure than on the EN rising-edge,
VID1 is in valid and correct state.
PVI - parallel interface
PVI is a 6-bit-wide parallel interface used to address the CORE section reference. According
to the selected code, the device sets the CORE section reference and regulates its output
voltage as reported into
NB section is always kept in HiZ; no activity is performed on this section. Furthermore,
PWROK information is ignored as well since the signal only applies to the SVI protocol.
PVI start-up
Once the PVI mode has been detected, the device uses the whole code available on the
VID[0:5] lines to define the reference for the CORE section. NB section is kept in HiZ.
Soft-start to the programmed reference is performed regardless of the state of PWROK.
See
Figure 6.
Section 6.10
System start-up: SVI (to metal-VID; left) and PVI (right)
for details about soft-start.
Table 6
.
Table 6
. NB section is kept in HiZ mode.
L6740L