LTC2923CDE#PBF Linear Technology, LTC2923CDE#PBF Datasheet - Page 11

• Manufacturer Part Number: LTC2923CDE#PBF
• Description: IC POWER SUPPLY CONTROLLER 12DFN
• Manufacturer: Linear Technology

Specifications of LTC2923CDE#PBF

• Applications: Power Supply Controller
• Voltage - Supply: 2.9 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 12-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Input: -
• Lead Free Status / Rohs Status: Compliant

APPLICATIO S I FOR ATIO
3-Step Design Procedure
The following 3-step procedure allows one to complete a
design for any of the tracking or sequencing profiles
shown in Figures 1 to 4. A basic three supply application
circuit is shown in Figure 9.
1. Set the ramp rate of the master signal .
2. Solve for the pair of resistors that provide the desired
Solve for the value of C
pin, based on the desired ramp rate (V/s) of the master
supply, S
If the external FET has a gate capacitance comparable to
C
reduced to compensate for the FET’s gate capacitance.
If no external FET is used, tie the GATE and RAMP pins
together.
ramp rate of the slave supply, assuming no delay .
Choose a ramp rate for the slave supply, S
supply ramps up coincident with the master supply or
with a fixed voltage offset, then the ramp rate equals the
master supply’s ramp rate. Be sure to use a fast enough
ramp rate for the slave supply so that it will finish
ramping before the master supply has reached its final
supply value. If not, the slave supply will be held below
the intended regulation value by the master supply. Use
the following formulas to determine the resistor values
for the desired ramp rate, where R
feedback resistors in the slave supply and V
feedback reference voltage of the slave supply:
where V
GATE
R
R
C
GATE
TB
TA
, then the external capacitor’s value should be
′ =
=
TRACK
M
R
=
.
R
FB
V
I
FB
FB
GATE
S
•
M
≈ 0.8V.
S
+
S
U
M
S
R
V
V
where I
TRACK
FB
FA
–
U
GATE
V
TRACK
R
GATE
, the capacitor on the GATE
TB
W
≈
10
FB
µ
A
and R
S
. If the slave
U
FA
FB
are the
is the
(1)
(2)
(3)
3. Choose R
As noted in step 2, small delays and large ratios of slave
ramp rate to master ramp rate (usually only seen in
sequencing) may result in solutions with negative values
for R
or the ratio of slave ramp rate to master ramp rate must be
reduced.
V
IN
Note that large ratios of slave ramp rate to master ramp
rate, S
sufficiently large delay is used in step 3, R
positive, otherwise S
If no delay is required, such as in coincident and
ratiometric tracking, then simply set R
delay is desired, as in offset tracking and supply se-
quencing, calculate R
where t
the parallel combination of R
TA
R
R
R
R
R
R
TB1
TA1
ONB
ONA
TA
. In such cases, either the delay must be increased
TA
S
′′ =
= R
D
R
R
/S
TB2
TA2
0.1µF
is the desired delay in seconds.
TA
M
Figure 9. Three Supply Application
TA
V
, may result in negative values for R
ON
RAMPBUF
TRACK1
TRACK2
V
to obtain the desired delay .
′||R
TRACK
CC
t
D
10Ω
TA
•
LTC2923
GATE
′′
GND
S
Q1
•
M
R
C
S
TA
GATE
/S
TB
′′ to determine the value of R
M
RAMP
FB1
FB2
must be reduced.
TA
MASTER
′ and R
R
R
2923 F09
FB
FB
FA1
FA2
DC/DC
DC/DC
LTC2923
R
R
V
V
IN
IN
FB2
FB1
TA
IN
IN
TA
′′
OUT
OUT
= R
TA
TA
11
will be
′. If a
TA
SLAVE1
SLAVE2
2923fa
′. If
(4)
(5)
TA