LTC2923CDE#PBF Linear Technology, LTC2923CDE#PBF Datasheet - Page 10

• Manufacturer Part Number: LTC2923CDE#PBF
• Description: IC POWER SUPPLY CONTROLLER 12DFN
• Manufacturer: Linear Technology

Specifications of LTC2923CDE#PBF

• Applications: Power Supply Controller
• Voltage - Supply: 2.9 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 12-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Input: -
• Lead Free Status / Rohs Status: Compliant

APPLICATIO S I FOR ATIO
LTC2923
Shutdown Output
In some applications it might be necessary to control the
shutdown or RUN/SS pins of the slave supplies using the
12-lead LTC2923CDE or LTC2923IDE. The LTC2923 may
not be able to supply the rated 1mA of current from the FB1
and FB2 pins when V
supplies are capable of operating at low input voltages,
use the open-drain SDO output to drive the SHDN or
RUN/SS pins of the slave supplies (see Figure 7). This will
hold the slave supplies’ outputs low until the ON pin is
above 1.23V, V
condition and there are no short-circuit faults latched. It
pulls low again when the ON pin is pulled below 1.23V and
the RAMP pin is below about 100mV. When two supplies
3.3V
16.5k
10
R
R
V
13k
TB1
TA1
IN
R
887k
R
412k
R
138k
R
100k
TB2
TA2
ONB
ONA
0.1µF
ON
RAMPBUF
TRACK1
TRACK2
V
CC
CC
10Ω
is above the 2.6V undervoltage lockout
LTC2923
U
GATE
GND
Q1
CC
C
10nF
GATE
is below 2.9V. If the slave power
STATUS
Figure 7
U
RAMP
SDO
FB1
FB2
V
3.3V
IN
R
10k
W
STATUS
R
35.7k
R
412k
2923 F07
RUN/SS
FB = 1.235V
RUN/SS
FB = 0.8V
FA1
FA2
DC/DC
DC/DC
16.5k
R
887k
R
V
V
IN
IN
FB2
FB1
IN
IN
U
OUT
OUT
1.8V
2.5V
3.3V
must have their RUN/SS or SHDN pins controlled indepen-
dently, tie a Schottky diode between each pin and the SDO
output (see Figure 8).
Status Output
The STATUS pin provides an indication that the supplies
are finished ramping up. This pin is an open-drain output
that pulls low until the GATE has been fully charged. Since
the GATE pin drives the gate of the external FET, or the
RAMP pin directly when no FET is used, the supplies are
completely ramped up when the GATE pin is fully charged.
It will go low again when the GATE pin is pulled low, either
because of a short-circuit fault or because the ON pin has
been pulled low.
16.5k
V
R
R
13k
IN
TB1
TA1
R
138k
R
100k
R
887k
R
412k
ONB
ONA
TB2
TA2
0.1µF
ON
RAMPBUF
TRACK1
TRACK2
V
CC
10Ω
LTC2923
GATE
GND
Q1
C
10nF
GATE
STATUS
Figure 8
RAMP
SDO
FB2
FB1
V
IN
3.3V
R
10k
STATUS
R
35.7k
R
412k
2923 F08
RUN/SS
FB = 1.235V
RUN/SS
FB = 0.8V
FA1
FA2
DC/DC
DC/DC
16.5k
R
887k
R
V
V
IN
IN
FB2
FB1
IN
IN
OUT
OUT
2923fa
1.8V
2.5V