DS1874T+ Maxim Integrated Products, DS1874T+ Datasheet - Page 20

IC CTLR SFP+ ANLG LDD 28-TQFN

DS1874T+

Manufacturer Part Number
DS1874T+
Description
IC CTLR SFP+ ANLG LDD 28-TQFN
Manufacturer
Maxim Integrated Products
Type
Laser Diode Controllerr
Datasheet

Specifications of DS1874T+

Number Of Channels
1
Voltage - Supply
2.85 V ~ 3.9 V
Current - Supply
2.5mA
Operating Temperature
-40°C ~ 95°C
Package / Case
28-WFQFN Exposed Pad
Mounting Type
Surface Mount
Number Of Outputs
5
Duty Cycle (max)
50 %
Output Voltage
0 V to 3.9 V
Mounting Style
SMD/SMT
Switching Frequency
0 KHz to 400 KHz
Operating Supply Voltage
2.85 V to 3.9 V
Supply Current
2.5 mA to 10 mA
Maximum Operating Temperature
+ 95 C
Fall Time
300 ns
Minimum Operating Temperature
- 40 C
Rise Time
300 ns
Synchronous Pin
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
90-1874T+000
SFP+ Controller with Digital LDD Interface
Figure 9. Recommended RC Filter for DAC1/DAC2
Figure 10. Delta-Sigma Outputs
Figure 11. DAC1/DAC2 LUT Assignments
20
______________________________________________________________________________________
DS1874
DAC1/DAC2
0
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
0
-40
LUT LOADED TO [7:0]
3.24kΩ
DAC[1/2]TC = 0
DAC[1/2]TI
TEMPERATURE (°C)
0.01μF
3.24kΩ
LUT LOADED TO [8:1]
(DAC BIT 0 = 0)
0.01μF
OUTPUT
+102
is either manually controlled or controlled using a tem-
perature-indexed LUT. A delta-sigma is a digital output
using pulse-density modulation. It provides much lower
output ripple than a standard digital PWM output given
the same clock rate and filter components. Before t
the DAC1 and DAC2 outputs are high impedance.
The external RC filter components are chosen based
on ripple requirements, output load, delta-sigma fre-
quency, and desired response time. A recommended
filter is shown in Figure 9.
The DS1874’s delta-sigma outputs are 9 bits. For illus-
trative purposes, a 3-bit example is provided. Each
possible output of this 3-bit delta-sigma DAC is given in
Figure 10.
In LUT mode, DAC1 and DAC2 are each controlled by a
separate 8-bit, 4°C-resolution, temperature-addressed
LUT. The delta-sigma outputs use a 9-bit structure. The
8-bit LUTs are either loaded directly into the MSBs (8:1)
or the LSBs (7:0). This is determined by DAC1TI (Table
02h, Register C3h), DAC2TI (Table 02h, Register C4h),
DAC1TC (Table 02h, Register C6h, bit 6), and DAC2TC
(Table 02h, Register C6h, bit 5). See Figure 11 for more
details. The DAC1 LUT (Table 07h) and DAC2 LUT
(Table 08h) are nonvolatile and password-2 protected.
The reference input, REFIN, is the supply voltage for
the output buffer of DAC1 and DAC2. The voltage con-
nected to REFIN must be able to support the edge rate
requirements of the delta-sigma outputs. In a typical
application, a 0.1µF capacitor should be connected
between REFIN and ground.
8
7
6
5
4
3
2
1
0
-40
LUT LOADED TO [8:1]
(DAC BIT 0 = 0)
DAC[1/2]TI
TEMPERATURE (°C)
LUT LOADED TO [7:0]
DAC[1/2]TC = 1
+102
INIT
,

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