DS1874T+ Maxim Integrated Products, DS1874T+ Datasheet
DS1874T+
Specifications of DS1874T+
Related parts for DS1874T+
DS1874T+ Summary of contents
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... Operating Temperature Range 11 MON4 ♦ 28-Pin TQFN (5mm x 5mm) Package 10 TXDOUT 9 RSEL 8 GND PART 7 DS1874T+ DS1874T+T&R + Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel Exposed pad. Features , CC Ordering Information TEMP RANGE PIN-PACKAGE -40°C to +95°C 28 TQFN-EP* -40°C to +95°C ...
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SFP+ Controller with Digital LDD Interface Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SFP+ Controller with Digital LDD Interface TABLE OF CONTENTS (continued) Transmit Fault (TXF) Output . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SFP+ Controller with Digital LDD Interface Figure 1. Modulation LUT Loading to MAX3798/MAX3799 MOD DAC . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SFP+ Controller with Digital LDD Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on MON1–MON4, RSEL, IN1, LOS, TXF, and TXD Pins Relative to Ground .................................-0. Voltage Range SDA, SCL, OUT1, CC RSELOUT, and LOSOUT Pins Relative ...
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SFP+ Controller with Digital LDD Interface DAC1, DAC2 ELECTRICAL CHARACTERISTICS (V = +2.85V to +3.9V -40°C to +95°C, unless otherwise noted PARAMETER SYMBOL Main Oscillator Frequency Delta-Sigma Input-Clock Frequency Reference Voltage Input (REFIN) V Output Range ...
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SFP+ Controller with Digital LDD Interface DIGITAL THERMOMETER CHARACTERISTICS (V = +2.85V to +3.9V -40°C to +95°C, unless otherwise noted PARAMETER SYMBOL Thermometer Error T AC ELECTRICAL CHARACTERISTICS (V = +2.85V to +3.9V -40°C ...
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SFP+ Controller with Digital LDD Interface ELECTRICAL CHARACTERISTICS (V = +2.85V to +3.9V -40°C to +95°C, timing referenced PARAMETER SCL Clock Frequency Clock Pulse-Width Low Clock Pulse-Width High Bus-Free Time ...
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SFP+ Controller with Digital LDD Interface (V = +2.85V to +3.9V +25°C, unless otherwise noted SUPPLY CURRENT vs. SUPPLY VOLTAGE SDA = SCL = V 2.9 CC 2.7 +95°C 2.5 2.3 -40°C 2.1 +25°C 1.9 1.7 ...
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SFP+ Controller with Digital LDD Interface PIN NAME 1 RSELOUT Rate-Select Output 2 2 SCL I C Serial-Clock Input 2 3 SDA I C Serial-Data Input/Output 4 TXF Transmit-Fault Input and Output. The output is open drain. 5 LOS Loss-of-Signal ...
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SFP+ Controller with Digital LDD Interface SDA INTERFACE SCL EEPROM 256 BYTES AT A0h V CC MON1 MON2 MON3P MON3N MON4 TEMPERATURE SENSOR TXD RSEL SEE IN1 FIGURE 13 LOS ______________________________________________________________________________________ MAIN MEMORY ...
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SFP+ Controller with Digital LDD Interface +3.3V 100Ω PIN-ROSA VCSEL-TOSA R BD Detailed Description The DS1874 integrates the control and monitoring func- tionality required to implement a VCSEL-based SFP or SFP+ system using Maxim’s MAX3798/MAX3799 com- bined limiting amplifier and ...
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SFP+ Controller with Digital LDD Interface Table 1. Acronyms ACRONYM DEFINITION ADC Analog-to-Digital Converter AGC Automatic Gain Control APC Automatic Power Control APD Avalanche Photodiode ATB Alarm Trap Bytes BM Burst Mode DAC Digital-to-Analog Converter LOS Loss of Signal LUT ...
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SFP+ Controller with Digital LDD Interface BIAS and MODULATION Control During Power-Up The DS1874 has two internal registers, MODULATION and BIAS, that represent the values written to the MAX3798/MAX3799’s modulation DAC and bias DAC through the 3-wire interface. On power-up, ...
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SFP+ Controller with Digital LDD Interface BIAS and MODULATION Registers as a Function of Transmit Disable (TXD) If TXD is asserted (logic 1) during normal operation, the outputs are disabled within t . When TXD is deassert- OFF ed (logic ...
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SFP+ Controller with Digital LDD Interface ignored until the end of the 3-wire communication that updates the MAX3798/MAX3799’s BIAS DAC, plus an additional 16 sample periods (t REP Monitors and Fault Detection Monitoring functions on the DS1874 include five quick-trip ...
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SFP+ Controller with Digital LDD Interface ONE ROUND-ROBIN ADC CYCLE TEMP NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND V IS ABOVE THE V ALARM LOW THRESHOLD. CC Figure 5. ...
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SFP+ Controller with Digital LDD Interface MON3 TIMESLICE PERFORM FINE- MODE CONVERSION DID PRIOR MON3 Y TIMESLICE RESULT IN A COARSE CONVERSION? (LAST RSSIR = 1 DID CURRENT FINE- Y MODE CONVERSION REACH MAX? N LAST RSSI = ...
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SFP+ Controller with Digital LDD Interface Low-Voltage Operation The DS1874 contains two power-on reset (POR) levels. The lower level is a digital POR (POD) and the higher level is an analog POR (POA). At startup, before the supply voltage rises ...
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SFP+ Controller with Digital LDD Interface 3.24kΩ 3.24kΩ DAC1/DAC2 0.01μF DS1874 Figure 9. Recommended RC Filter for DAC1/DAC2 Figure 10. Delta-Sigma Outputs DAC[1/2]TI 8 DAC[1/2] LUT ...
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SFP+ Controller with Digital LDD Interface Five digital input and five digital output pins are provid- ed for monitoring and control. By default (LOSC = 1, Table 02h, Register 89h), the LOS pin is used to convert a standard comparator ...
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SFP+ Controller with Digital LDD Interface IN1S INVOUT1 IN1C IN1 RSELS RSELC RSEL LOSC INV LOS LOS MUX LOS LO RXL Figure 13. Logic Diagram 2 same signals and faults can also be used to generate the internal signal FETG ...
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SFP+ Controller with Digital LDD Interface after the CSELOUT has been set to 1. Each operation consists of 16-bit transfers (15-bit address/data, 1-bit RWN). All data transfers are MSB first. BIT NAME DESCRIPTION 15:9 Address 7-bit internal register address 8 ...
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SFP+ Controller with Digital LDD Interface POR READ TXPOR1 YES TX_POR = 1? NO SET TXD FLAG HERE WRITE MOD, BIAS = 00 TXD_LATCHED = 1 UPDATE CTRL NO TXD = = 0? YES YES SET RTXPOR2_FLAG HERE READ TXPOR2 ...
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SFP+ Controller with Digital LDD Interface During initialization, the DS1874 transfers all its 3-wire EEPROM control registers to the MAX3798/MAX3799. The 3-wire control registers include the following: • RXCTRL1 • RXCTRL2 • SET_CML • SET_LOS • TXCTRL • IMODMAX MAX3798/MAX3799 ...
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SFP+ Controller with Digital LDD Interface Communication The following terminology is commonly used to 2 describe I C data transfers. Master device: The master device controls the slave devices on the bus. The master device gen- erates ...
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SFP+ Controller with Digital LDD Interface sequence indication that the device is not receiving data. Byte write: A byte write consists of 8 bits of informa- tion transferred from the master to the slave (most significant bit ...
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SFP+ Controller with Digital LDD Interface 2 TYPICAL I C WRITE TRANSACTION MSB LSB START R/W SLAVE READ/ ADDRESS* WRITE *IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY ...
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SFP+ Controller with Digital LDD Interface Table 05h is empty by default. It can be configured to contain the alarm- and warning-enable bytes from Table 01h, Registers F8h–FFh with the MASK bit enabled (Table 02h, Register 89h). In this case ...
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SFP+ Controller with Digital LDD Interface The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is locat memory at the row address (hexadecimal) in the ...
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SFP+ Controller with Digital LDD Interface WORD 0 ROW ROW (hex) NAME BYTE 0/8 <7> 80–BF EEPROM EE <8> C0–F7 EEPROM EE <8> ALARM ALARM F8 ENABLE EN 3 The ALARM ENABLE bytes (Registers F8h–FFh) can be configured to exist ...
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SFP+ Controller with Digital LDD Interface WORD 0 ROW ROW (hex) NAME BYTE 0/8 <0> <8> <4> 80 CONFIG MODE 0 SAMPLE <8> 88 CONFIG 1 RATE <8> 90 SCALE RESERVED 0 <8> 98 SCALE MON3 FINE SCALE 1 <8> ...
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SFP+ Controller with Digital LDD Interface WORD 0 ROW ROW (hex) NAME BYTE 0/8 <8> 80–C7 LUT4 MOD WORD 0 ROW ROW (hex) NAME BYTE 0/8 80–F7 EMPTY EMPTY <8> ALARM ALARM F8 ENABLE EN 3 Table 05h is empty ...
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SFP+ Controller with Digital LDD Interface WORD 0 ROW ROW (hex) NAME BYTE 0/8 <8> 80–9F LUT7 DAC1 <8> A0 LUT7 DAC1 WORD 0 ROW ROW (hex) NAME BYTE 0/8 <8> 80–9F LUT8 DAC2 <8> A0 LUT8 DAC2 WORD 0 ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 00h–01h: TEMP ALARM HI Lower Memory, Register 04h–05h: TEMP WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 6 00h, 04h 01h, 05h 2 2 BIT ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 08h–09h: V Lower Memory, Register 0Ch–0Dh: V Lower Memory, Register 10h–11h: MON1 ALARM HI Lower Memory, Register 14h–15h: MON1 WARN HI Lower Memory, Register 18h–19h: MON2 ALARM HI Lower Memory, Register ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 0Ah–0Bh: V Lower Memory, Register 0Eh–0Fh: V Lower Memory, Register 12h–13h: MON1 ALARM LO Lower Memory, Register 16h–17h: MON1 WARN LO Lower Memory, Register 1Ah–1Bh: MON2 ALARM LO Lower Memory, Register ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 30h–5Fh: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 30h to 5Fh EE EE BIT 7 PW2 level access-controlled EEPROM. Lower Memory, Register 60h–61h: TEMP VALUE POWER-ON VALUE READ ACCESS ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 62h–63h VALUE Lower Memory, Register 64h–65h: MON1 VALUE Lower Memory, Register 66h–67h: MON2 VALUE Lower Memory, Register 68h–69h: MON3 VALUE Lower Memory, Register 6Ah–6Bh: MON4 VALUE POWER-ON VALUE READ ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 6Eh: STATUS POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE Write Access N/A All 6Eh TXDS TXDC BIT 7 TXDS: TXD Status Bit. Reflects the logic state of the TXD pin ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 6Fh: UPDATE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 6Fh TEMP RDY VCC RDY BIT 7 Update of completed conversions. At power-on, these bits are cleared and are set as ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 70h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 70h TEMP HI TEMP LO BIT 7 TEMP HI: High-alarm status for temperature measurement. BIT (Default) Last measurement ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 71h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 71h MON3 HI MON3 LO BIT 7 MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 72h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 72h RESERVED RESERVED BIT 7 BITS 7:4 RESERVED HBAL: High-Bias Alarm Status; Fast Comparison. A TXD event clears this alarm. 0 ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 74h: WARN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 74h TEMP HI TEMP LO BIT 7 TEMP HI: High-warning status for temperature measurement. BIT (Default) Last measurement ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 75h: WARN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 75h MON3 HI MON3 LO BIT 7 MON3 HI: High-warning status for MON3 measurement. BIT (Default) Last measurement ...
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SFP+ Controller with Digital LDD Interface Lower Memory, Register 7Bh–7Eh: Password Entry (PWE) POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 31 30 7Bh 7Ch 7Dh 7Eh 2 ...
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SFP+ Controller with Digital LDD Interface Table 01h, Register 80h–BFh: EEPROM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h–BFh EE EE BIT 7 EEPROM for PW1 and/or PW2 level access. Table 01h, Register C0h–F7h: EEPROM POWER-ON VALUE READ ACCESS ...
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SFP+ Controller with Digital LDD Interface Table 01h, Register F8h: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F8h TEMP HI TEMP LO BIT 7 Layout is identical to ALARM Register 71h) logic. The MASK bit (Table 02h, ...
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SFP+ Controller with Digital LDD Interface Table 01h, Register F9h: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F9h MON3 HI MON3 LO BIT 7 Layout is identical to ALARM Register 71h) logic. The MASK bit (Table 02h, ...
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SFP+ Controller with Digital LDD Interface Table 01h, Register FAh: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FAh RESERVED RESERVED BIT 7 Layout is identical to ALARM Figure 12) logic. The MASK bit (Table 02h, Register 89h) ...
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SFP+ Controller with Digital LDD Interface Table 01h, Register FBh: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE FBh LOS HI LOS LO BIT 7 Layout is identical to ALARM whether this memory exists in Table 01h or ...
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SFP+ Controller with Digital LDD Interface Table 01h, Register FCh: WARN EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F8h TEMP HI TEMP LO BIT 7 Layout is identical to WARN Register 71h) logic. The MASK bit (Table 02h, ...
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SFP+ Controller with Digital LDD Interface Table 01h, Register FDh: WARN EN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE F9h MON3 HI MON3 LO BIT 7 Layout is identical to WARN Register 71h) logic. The MASK bit (Table 02h, ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register 80h: MODE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h SEEB RESERVED BIT 7 SEEB (Default) Enables EEPROM writes to SEE bytes. BIT Disables EEPROM ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register 81h: Temperature Index (TINDEX) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 81h 2 2 BIT 7 Holds the calculated index based on the temperature measurement. This index is ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register 84h–85h: DAC1 VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 84h 85h 2 2 BIT 7 The digital value used for DAC1 and recalled from Table ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register 88h: SAMPLE RATE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 88h SEE SEE BIT 7 BITS 7:3 SEE APC_SR[2:0]: 3-bit sample rate for comparison of APC control. Defines the sample ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register 89h: CNFGA FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 89h LOSC RESERVED BIT 7 LOSC: LOS Configuration. Defines the source for the LOSOUT pin (see Figure 13). BIT 7 0 ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register 8Ah: CNFGB FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Ah IN1C INVOUT1 BIT 7 IN1C: IN1 Software Control Bit (see Figure 13). BIT IN1 pin’s logic controls ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register 8Bh: CNFGC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8Bh RESERVED RESERVED BIT 7 BITS 7:6 RESERVED TXDM34: Enables TXD to reset alarms and warnings associated to MON3 and MON4 ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register 8Dh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE This register is reserved. Table 02h, Register 8Eh: RIGHT-SHIFT 1 (RSHIFT 1 ) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register 90h–91h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. Table 02h, Register 92h–93h SCALE Table 02h, Register 94h–95h: MON1 SCALE Table 02h, Register 96h–97h: ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register A2h–A3h OFFSET Table 02h, Register A4h–A5h: MON1 OFFSET Table 02h, Register A6h–A7h: MON2 OFFSET Table 02h, Register A8h–A9h: MON3 FINE OFFSET Table 02h, Register AAh–ABh: MON4 OFFSET Table 02h, ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register B0h–B3h: PW1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 31 30 B0h B1h B2h B3h 2 2 BIT ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register B8h: LOS RANGING FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B8h RESERVED HLOS 2 BIT 7 This register controls the full-scale range of the quick-trip monitoring for the differential input’s ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register B9h: COMP RANGING FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B9h RESERVED BIAS 2 BIT 7 The upper nibble of this byte controls the full-scale range of the quick-trip monitoring ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register BAh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE This register is reserved. Table 02h, Register BBh: ISTEP FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8 7 BBh 2 ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register BDh: LTXP FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 BDh 2 2 BIT 7 Fast-comparison DAC threshold adjust for low TXP. This value is subtracted from the APC ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register C0h: PW_ENA FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C0h RWTBL78 RWTBL1C BIT 7 RWTBL78: Tables 07h–08h BIT (Default) Read and write access for PW2 only. 1 ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register C1h: PW_ENB FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C1h RWTBL46 RTBL1C BIT 7 RWTBL46: Read and Write Tables 04h, 06h BIT (Default) Read and write access ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register C2h: MODTI FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 C2h 2 2 BIT 7 The modulation temperature index defines the TempCo boundary for the MODULATION LUT. The MODTC ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register C4h: DAC2TI FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 C4h 2 2 BIT 7 DAC2 temperature index defines the TempCo boundary for the DAC2 LUT. The DAC2TC bit ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register C6h: LUTTC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE C6h MODTC DAC1TC BIT 7 MODTC: Modulation TempCo 0 = Negative TempCo. For a TINDEX below the MODTI value, the 8-bit ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register C7h: TBLSELPON FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 C7h 2 2 BIT 7 Chooses the initial value for the table-select byte (Lower Memory, Register 7Fh) at power-on. ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register CBh–CCh: BIAS REGISTER FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE CBh RESERVED RESERVED 7 6 CCh 2 2 BIT 7 The digital value used for BIAS and resolved from the ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register CFh: DEVICE VER FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE CFh BIT 7 Hardwired connections to show the device version. Table 02h, Register D0h–D7h: HBATH FACTORY DEFAULT READ ACCESS WRITE ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register D8h–E7h: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers do not exist. Table 02h, Register E8h: RXCTRL1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 E8h ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register EAh: SETCML FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 EAh 2 2 BIT 7 MAX3798/MAX3799 register. After either V bit is set high (visible in 3W TXSTAT1, Bit ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register EDh: IMODMAX FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 EDh 2 2 BIT 7 MAX3798/MAX3799 register. After either V bit is set high (visible in 3W TXSTAT1, Bit ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register EFh: SETPWCTRL FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 EFh 2 2 BIT 7 MAX3798/MAX3799 register. After either V bit is set high (visible in 3W TXSTAT1, Bit ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register F8h: 3WCTRL FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE F8h RESERVED RESERVED BIT 7 BITS 7:2 RESERVED 3WRW: Initiates a 3-wire write or read operation. The write command uses the ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register FAh: WRITE FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 FAh 2 2 BIT 7 This byte is used during manual 3-wire communication. When a manual write is initiated, ...
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SFP+ Controller with Digital LDD Interface Table 02h, Register FDh: TXSTAT2 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 FDh 2 2 BIT 7 MAX3798/MAX3799 register. This value is read from the MAX3798/MAX3799 with the 3-wire interface every ...
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SFP+ Controller with Digital LDD Interface Table 06h, Register 80h–A3h: APC LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80h–A3h 2 2 BIT 7 The APC LUT is a set of registers assigned to hold the temperature ...
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SFP+ Controller with Digital LDD Interface Table 07h, Register 80h–A3h: DAC1 LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80h–A3h 2 2 BIT 7 The DAC1 LUT is a set of registers assigned to hold the PWM ...
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SFP+ Controller with Digital LDD Interface Table 08h, Register 80h–A3h: DAC2 LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 7 6 80h–A3h 2 2 BIT 7 The DAC2 LUT is set of registers assigned to hold the PWM profile ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 88 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products ...