FSDM07652RWDTU Fairchild Semiconductor, FSDM07652RWDTU Datasheet - Page 11

• Manufacturer Part Number: FSDM07652RWDTU
• Description: IC SWIT PWM GREEN CM HV TO220F
• Manufacturer: Fairchild Semiconductor

Specifications of FSDM07652RWDTU

• Output Isolation: Isolated
• Frequency Range: 60 ~ 72kHz
• Voltage - Input: 8 ~ 20 V
• Voltage - Output: 650V
• Power (watts): 80W
• Operating Temperature: 25°C ~ 150°C
• Package / Case: TO-220-6 Full Pack Formed Leads
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FSDM07652RWDTU_NL; FSDM07652RWDTU_NL

Functional Description
1. 1. 1. 1. Startup : In previous generations of Fairchild Power
Switches (FPS
resistor to the DC input voltage line. In this generation the
startup resistor is replaced by an internal high voltage current
source. At startup, an internal high voltage current source
supplies the internal bias and charges the external capacitor
(C
4. When Vcc reaches 12V, the FPS
the internal high voltage current source is disabled. Then, the
FPS
power is supplied from the auxiliary transformer winding
unless Vcc goes below the stop voltage of 8V.
2. Feedback Control : FSDM07652R employs current
mode control, as shown in figure 5. An opto-coupler (such as
the H11A817A) and shunt regulator (such as the KA431) are
typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across the
Rsense resistor plus an offset voltage makes it possible to
control the switching duty cycle. When the reference pin
voltage of the KA431 exceeds the internal reference voltage
of 2.5V, the H11A817A LED current increases, thus pulling
down the feedback voltage and reducing the duty cycle. This
event typically happens when the input voltage is increased
or the output load is decreased.
vcc
TM
) that is connected to the Vcc pin as illustrated in figure
8V/12V
continues its normal switching operation and the
Figure 4. Internal startup circuit
3
TM
Vcc
) the Vcc pin had an external start-up
C
Vcc
Vcc good
TM
begins switching and
I
start
Internal
Vref
Bias
6
Vstr
V
DC
2.1 Pulse-by-pulse current limit: Because current mode
control is employed, the peak current through the Sense FET
is limited by the inverting input of PWM comparator (Vfb*)
as shown in figure 5. Assuming that the 0.9mA current
source flows only through the internal resistor (2.5R +R= 2.8
k ), the cathode voltage of diode D2 is about 2.5V. Since D1
is blocked when the feedback voltage (Vfb) exceeds 2.5V,
the maximum voltage of the cathode of D2 is clamped at this
voltage, thus clamping Vfb*. Therefore, the peak value of
the current through the Sense FET is limited.
2.2 Leading edge blanking (LEB) : At the instant the
internal Sense FET is turned on, there usually exists a high
current spike through the Sense FET, caused by primary-side
capacitance and secondary-side rectifier reverse recovery.
Excessive voltage across the Rsense resistor would lead to
incorrect feedback operation in the current mode PWM
control. To counter this effect, the FPS
edge blanking (LEB) circuit. This circuit inhibits the PWM
comparator for a short time (T
turned on.
3. Protection Circuit : The FSDM07652R has several self
protective functions such as over load protection (OLP),
abnormal over current protection (AOCP), over voltage
protection (OVP) and thermal shutdown (TSD). Because
these protection circuits are fully integrated into the IC
without external components, the reliability can be improved
without increasing cost. Once the fault condition occurs,
switching is terminated and the Sense FET remains off. This
causes Vcc to fall. When Vcc reaches the UVLO stop
voltage, 8V, the protection is reset and the internal high
voltage current source charges the Vcc capacitor via the Vstr
pin. When Vcc reaches the UVLO start voltage,12V, the
FPS
auto-restart can alternately enable and disable the switching
of the power Sense FET until the fault condition is
eliminated (see figure 6).
Vo
TM
Figure 5. Pulse width modulation (PWM) circuit
H11A817A
resumes its normal operation. In this manner, the
KA431
Vfb
C
B
4
I
delay
V
Vcc
SD
D1
Vref
I
V
FB
D2
+
LEB
fb
-
*
2.5R
R
) after the Sense FET is
OSC
TM
OLP
employs a leading
driver
Gate
FSDM07652R
R
SenseFET
sense
11