FSQ500L Fairchild Semiconductor, FSQ500L Datasheet - Page 8

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FSQ500L

Manufacturer Part Number
FSQ500L
Description
IC SWIT PWM GREEN UVLO SOT223
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of FSQ500L

Output Isolation
Isolated
Frequency Range
120 ~ 140kHz
Voltage - Input
5 ~ 10 V
Voltage - Output
700V
Power (watts)
3W
Operating Temperature
-40°C ~ 125°C
Package / Case
TO-261-4, TO-261AA, SOT-223-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FSQ500L
Manufacturer:
CYRESS
Quantity:
772
© 2008 Fairchild Semiconductor Corporation
FSQ500L • Rev. 1.0.1
Functional Description
1. Startup and V
high-voltage current source supplies the internal bias
and charges the external capacitor (C
the V
voltage regulator (HV/REG) located between the D and
V
operating current. Therefore, FSQ500L needs no
auxiliary bias winding.
2. Feedback Control: FSQ500L employs current mode
control, as shown in Figure 16. An opto-coupler (such
as the FOD817A) and shunt regulator (such as the
KA431) are typically used to implement the feedback
network. Comparing the feedback voltage with the
voltage across the R
control the switching duty cycle. When the reference pin
voltage of the regulator exceeds the internal reference
voltage
increases, pulling down the feedback voltage and
reducing the duty cycle. This typically happens when
the line input voltage increases or the output load
current decreases.
2.1 Pulse-by-Pulse Current Limit: Because current
mode control is employed, the peak current through the
senseFET is limited by the non-inverting input of PWM
comparator (V
that 225µA current source flows only through the
internal resistor (8R + R = 12kΩ), the cathode voltage
of diode D2 is about 2.7V. Since D1 is blocked when
the feedback voltage (V
voltage of the cathode of D2 is clamped at this voltage,
clamping V
through the senseFET is limited.
2.2 Leading-Edge Blanking (LEB): At the instant the
internal senseFET is turned on, a high-current spike
occurs through the senseFET, caused by primary-side
capacitance
recovery. Excessive voltage across the R
would lead to incorrect feedback operation in the
current mode PWM control. To counter this effect, the
FPS employs a leading-edge blanking (LEB) circuit.
This circuit inhibits the PWM comparator for a short
time (t
CC
C
pins regulates the V
CC
LEB
A
V
pin, as illustrated in Figure 15. An internal high-
CC
of
= 250ns) after the senseFET turns on.
FB
*. Therefore, the peak value of the current
2.5V,
3
and
FB
Figure 15. Startup Block
*), as shown in Figure 16. Assuming
CC
6.5V
Transformer
secondary-side
Regulation: At startup, an internal
V
sense
the
REF
FB
) exceeds 2.7V, the maximum
I
I
CC
CH
resistor makes it possible to
START
opto-coupler
to be 6.5V and supplies
UVLO
HV/REG
rectifier
A
) connected to
D
LED
sense
2
reverse
resistor
current
8
3. Protection Circuits: The FSQ500L has two self-
protective functions: overload protection (OLP) and
thermal shutdown (TSD). While OLP is implemented as
auto-restart mode, there is no switching when TSD
triggers. Once the overload condition is detected,
switching is terminated, the senseFET remains off, and
HV/REG turns off. This causes V
falls below the under voltage lockout (UVLO) stop
voltage of 5.0V, the protection is reset and the startup
circuit charges the V
the start voltage of 6.0V, the FSQ500L resumes its
normal operation. If the fault condition is still not
removed, the senseFET and HV/REG remain off and
V
restart can alternately enable and disable the switching
of the power senseFET until the fault condition is
eliminated, as shown in Figure 17.
Because these protection circuits are fully integrated
into the IC without external components, reliability is
improved without increasing cost.
6.5V
6.0V
V
5.0V
V
CC
V
Figure 16. Pulse Width Modulation (PWM) Circuit
CC
DS
O
Figure 17. Auto Restart Protection Waveforms
drops to V
Power
FOD817A
on
KA431
operation
V
Normal
FB
STOP
C
B
2
occurs
OLP
V
again. In this manner, the auto-
CC
V
SD
CC
I
DELAY
D1
capacitor. When V
V
CC
V
I
FB
situation
D2
+
FB
-
Fault
*
R
8R
OSC
CC
OLP
to fall. When V
removed
OLP
driver
Gate
www.fairchildsemi.com
CC
R
sense
SenseFET
operation
Normal
reaches
CC
t

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