SG684965DZ Fairchild Semiconductor, SG684965DZ Datasheet - Page 11

• Manufacturer Part Number: SG684965DZ
• Description: IC CTRLR PWM OTP UVLO CV/CC 8DIP
• Manufacturer: Fairchild Semiconductor

Specifications of SG684965DZ

• Output Isolation: Isolated
• Frequency Range: 60 ~ 70kHz
• Voltage - Input: 8 ~ 25 V
• Voltage - Output: 16.7V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Outputs: 1
• Duty Cycle (max): 80 %
• Mounting Style: Through Hole
• Switching Frequency: 70 KHz
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

© 2008 Fairchild Semiconductor Corporation
SG6849 Rev. 1.6.1
Gate Output
The SG6849 BiCMOS output stage is a fast totem-pole
gate driver. Cross-conduction is avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
16.7V Zener diode to protect the power MOSFET
transistors against harmful over-voltage gate signals.
Slope Compensation
The sensed voltage across the current sense resistor is
used for current-mode control and pulse-by-pulse
current limiting. The built-in slope compensation
function improves power supply stability. Furthermore, it
prevents sub-harmonic oscillations that normally would
occur because of peak current mode control. A
positively sloped, synchronized ramp is activated by the
SG6849 with every switching cycle. The slope of the
ramp is:
0.36 ×
Duty(max.)
Duty
(1)
11
Noise Immunity
Noise from the current sense or the control signal may
cause significant pulse width jitter, particularly in
continuous-conduction
helps alleviate this problem. Good placement and
layout practices should be followed. Avoid long PCB
traces and component leads. Compensation and filter
components should be located near the SG6849.
Increasing the power-MOS gate resistance is advised.
mode.
Slope
compensation
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