PSD4235G2V-12UI STMicroelectronics, PSD4235G2V-12UI Datasheet - Page 96

• Manufacturer Part Number: PSD4235G2V-12UI
• Description: IC FLASH 4MBIT 120NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2V-12UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Number Of Macrocells: 24
• Maximum Operating Frequency: 25.6 MHz
• Delay Time: 90 ns
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1970

Power management
21.3
21.4
96/129
Figure 31. APD unit
Table 49.
1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the
2. Typical current consumption, see
Other power saving options
The PSD offers other reduced power saving options that are independent of the Power-
down mode. Except for PSD Chip Select input (CSI, PD2) features, they are enabled by
setting bits in PMMR0 and PMMR2 (as summarized in
PLD power management
The power and speed of the PLDs are controlled by the Turbo bit (Bit 3) in PMMR0. By
setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified standby
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time is increased after the Turbo bit is set to ’1’ (turned off) when the inputs change at
a composite frequency of less than 15 MHz. When the Turbo bit is reset to ’0’ (turned on),
the PLDs run at full power and speed. The Turbo bit affects the PLD’s DC power, AC power,
and propagation delay. See the AC and DC characteristics tables for PLD timing values
(seeTable
Blocking MCU control signals with the PMMR2 bits can further reduce PLD AC power
consumption.
Power-
down
Turbo bit.
Turbo bit is 0.
Mode
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
69).
Normal t
PSD timing and standby current during Power-down mode
PLD propagation
DISABLE Primary and Secondary
FLASH Memory and SRAM
TRANSITION
DETECTION
delay
DETECT
PD
EDGE
Table
access time
61, assuming no PLD inputs are changing state and the PLD
No Access
Memory
CLR
COUNTER
APD
PD
PD
Access recovery time to
normal access
Section 6.15
DISABLE BUS
INTERFACE
t
LVDV
PLD
and
Secondary Flash
Memory Select
Primary Flash
Memory Select
POWER DOWN
(PDN) Select
SRAM Select
Table
Typical standby
(1)
24).
PSD4235G2
current
I
SB
(2)
AI04939