PSD4235G2V-12UI STMicroelectronics, PSD4235G2V-12UI Datasheet - Page 23

• Manufacturer Part Number: PSD4235G2V-12UI
• Description: IC FLASH 4MBIT 120NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2V-12UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Number Of Macrocells: 24
• Maximum Operating Frequency: 25.6 MHz
• Delay Time: 90 ns
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1970

PSD4235G2
3.9
peripherals, or internal memory and I/O. The Page register can also be used to change the
address mapping of the Flash memory blocks into different memory spaces for IAP.
Power management unit (PMU)
The power management unit (PMU) gives the user control of the power consumption on
selected functional blocks based on system requirements. The PMU includes an Automatic
Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit
has a Power-down mode that helps reduce power consumption.
The PSD also has some bits that are configured at run-time by the MCU to reduce power
consumption of the CPLD. The Turbo bit in PMMR0 can be reset to ’0’ and the CPLD latches
its outputs and goes to Standby mode until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD
to reduce power consumption. See
details.
Table 5.
Primary Flash memory
Secondary Flash memory
PLD Array (DPLD and CPLD)
PSD configuration
Functional block
Methods of programming different functional blocks of the PSD
Section 21: Power management on page 94
JTAG-ISP
Yes
Yes
Yes
Yes
programmer
Device
PSD architectural overview
Yes
Yes
Yes
Yes
for more
IAP
Yes
Yes
No
No
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