MT48H32M16LFCJ-75 L IT:A TR Micron Technology Inc, MT48H32M16LFCJ-75 L IT:A TR Datasheet - Page 44

• Manufacturer Part Number: MT48H32M16LFCJ-75 L IT:A TR
• Description: IC SDRAM 512MBIT 133MHZ 54VBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H32M16LFCJ-75 L IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1331-2

Table 8:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
(auto precharge
(auto precharge
Current State
precharging
precharge)
precharge)
activating,
(with auto
(with auto
active, or
disabled)
disabled)
Write
Write
Read
Read
Row
Any
Idle
Truth Table – Current State Bank n, Command to Bank m
Notes: 1–6; notes appear below and on next page
Notes:
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted; i.e., the current state is
3. Current state definitions:
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued
RAS# CAS#
t
for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
Idle:
Row active:
Read:
Write:
Read w/auto-
precharge enabled:
Write w/auto-
precharge enabled:
when all banks are idle.
H
H
H
H
H
H
H
H
H
H
H
XSR has been met (if the previous state was self refresh).
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
WE#
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
Command (Action)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
The bank has been precharged, and
A row in the bank has been activated, and
data bursts/accesses and no register accesses are in progress.
has not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
A READ burst has been initiated, with auto precharge disabled, and
n-1
44
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RP has been met. Once
RP has been met. Once
n
is HIGH (Table 6 on page 41) and after
t
RP has been met.
©2005 Micron Technology, Inc. All rights reserved.
t
RCD has been met. No
t
t
RP is met, the bank
RP is met, the bank
Truth Tables
7, 13, 14
7, 13, 15
7, 13, 16
7, 13, 17
Notes
7, 11
7, 12
7, 8
7, 9
10
10
10
10
7
7