MT48H32M16LFCJ-75 L IT:A TR Micron Technology Inc, MT48H32M16LFCJ-75 L IT:A TR Datasheet - Page 36

• Manufacturer Part Number: MT48H32M16LFCJ-75 L IT:A TR
• Description: IC SDRAM 512MBIT 133MHZ 54VBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H32M16LFCJ-75 L IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1331-2

Figure 28:
Clock Suspend
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
COMMAND
CKE
CK
All Banks idle with no
activity on the data bus
Deep Power-Down
Notes:
NOP
T0
1. Maintain NOP input conditions for a minimum of 100µs.
2. Issue PRECHARGE commands for all banks.
3. Issue two or more AUTO REFRESH commands.
1. Clock must be stable prior to CKE going HIGH.
2. DPD = Deep power-down mode command; PRE ALL = Precharge all banks.
3. Exit of deep power-down mode must be followed by the sequence described in the Deep
In order to exit deep power-down mode, CKE must be asserted HIGH. After exiting, the
following sequence is needed in order to enter a new command:
The values of the mode register and extended mode register will be retained upon
exiting deep power-down.
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls at the time of
a suspended internal clock edge is ignored; any data present on the DQ balls remains
driven; and burst counters are not incremented, as long as the clock is suspended (see
examples in Figure 29 on page 37 and Figure 30 on page 37).
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
Power-Down” section on page 35.
t
IS
DPD
T1
Enter deep power-down mode
2
T2
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
(
(
(
)
(
)
(
t
)
)
)
(
CKE
(
(
(
)
)
(
)
)
)
36
Ta0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ta1
NOP
Exit deep power-down mode
T = 100µs
©2005 Micron Technology, Inc. All rights reserved.
Ta2
NOP
DON’T CARE
Operations
Vaild
Ta3
3