MT48H32M16LF Micron Semiconductor Products, MT48H32M16LF Datasheet
MT48H32M16LF
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MT48H32M16LF Summary of contents
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... Mobile SDRAM MT48H32M16LF – 8 Meg banks MT48H16M32LF/LG – 4 Meg banks Features • 1.7–1.95V / DD DD • Fully synchronous; all signals registered on positive edge of system clock • Internal, pipelined operation; column address can be changed every clock cycle • ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 512Mb Mobile SDRAM Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1: 512Mb Mobile SDRAM Part Numbering MT Micron Technology Product Family 48 = Mobile SDR SDRAM Operating Voltage H = 1.8V/1.8V Configuration 32 Meg Meg x 32 Addressing LF = Mobile standard addressing LG = Reduced ...
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Functional Block Diagrams Figure 2: 32 Meg x 16 SDRAM CKE CLK Control CS# logic WE# CAS# RAS# EXT mode register Refresh Mode register counter Address Address BA0, BA1 register PDF: 09005aef82ea3742/Source: 09005aef82ea371a 512mb_mobile_sdram_y47m__2.fm - Rev. B 4/08 EN 512Mb: ...
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Figure 3: 16 Meg x 32 SDRAM CKE CLK Control CS# logic WE# CAS# RAS# EXT mode register Mode register Address Address BA0, BA1 register PDF: 09005aef82ea3742/Source: 09005aef82ea371a 512mb_mobile_sdram_y47m__2.fm - Rev. B 4/08 EN 512Mb: 32 Meg x 16, 16 ...
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Ball Assignments Figure 4: 54-Ball VFBGA (Top View Notes: 1. The E2 pin must be connected to V PDF: 09005aef82ea3742/Source: 09005aef82ea371a 512mb_mobile_sdram_y47m__2.fm - Rev. B 4/08 EN 512Mb: 32 Meg x ...
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Figure 5: 90-Ball VFBGA (Top View Notes: 1. The K2 pin must be connected to V PDF: 09005aef82ea3742/Source: 09005aef82ea371a 512mb_mobile_sdram_y47m__2.fm - Rev. B 4/08 EN ...
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Ball Descriptions Table 3: VFBGA Ball Descriptions 54-Ball VFBGA 90-Ball VFBGA F7, F8, F9 K7, J9, K8 E8, F1 K9, K1, F8, F2 G7, G8 J7, H8 H7, H8, J8, J7, G8, G9, F7, ...
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Table 3: VFBGA Ball Descriptions (continued) 54-Ball VFBGA 90-Ball VFBGA A8, B9, B8, C9, R8, N7, R9, N8, C8, D9, D8, E9, P9, M8, M7, L8, E1, D2, D1, C2, L2, M3, M2, P1, C1, B2, B1, A2 N2, R1, ...
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Package Dimensions Figure 6: 54-Ball VFBGA (8mm x 9mm) Seating plane A 0.1 A 54X Ø0.45 Solder ball diameter refers to post reflow condition. The pre reflow balls are Ø0.42 on Ø0.4 SMD ball pads. 3.2 6.4 ...
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Figure 7: 90-Ball VFBGA (10mm x 13mm) Seating plane A 0.1 A 90X Ø0.45 Dimensions apply to solder balls post-reflow. The pre-reflow balls are Ø0.42 on Ø0 SMD ball pads. 5.6 11.2 0.8 TYP 3.2 Notes: 1. ...
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Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed in Table 4 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those ...
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Table 7: I Specifications and Conditions (x16) DD Note 1 applies to all parameters and conditions; notes appear on page 16; V Parameter/Condition Operating current: Active mode; Burst = 1; READ or WRITE; Standby current: Power-down mode; All banks idle; ...
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Table Specifications and Conditions (x16 and x32) DD Notes and 10 apply to all conditions and parameters; V Parameter/Condition Self refresh t t CKE = LOW (MIN); Address and control inputs ...
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Figure 8: Typical I 7 Curves DD 700 650 600 550 500 450 400 350 300 250 200 150 100 -40 -35 -30 -25 -20 -15 -10 -5 PDF: 09005aef82ea3742/Source: 09005aef82ea371a 512mb_mobile_sdram_y47m__2.fm - Rev. B 4/08 EN 512Mb: 32 Meg ...
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Table 10: Electrical Characteristics and Recommended AC Operating Conditions Notes 1–5 apply to all parameters; notes begin below Table 11 on page 19. AC Characteristics Parameter Access time from CLK (positive edge) Address hold time Address setup time CLK high-level ...
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Table 11: AC Functional Characteristics Notes 1–5 apply to all parameters Parameter Last data-in to burst STOP command READ/WRITE command to READ/WRITE command Last data-in to new READ/WRITE command CKE to clock disable or power-down entry mode Data-in to ACTIVE ...
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Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 13. Timing is specified by 14. Timing is specified by rate. 15. Timing is specified by 16. Based on PDF: 09005aef82ea3742/Source: 09005aef82ea371a 512mb_mobile_sdram_y47m__2.fm - ...
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Table 12: Target Output Drive Characteristics (Full Strength) Notes 1–2 apply to all values. Characteristics are specified under best and worst process variations/conditions Pull-Down Current (mA) Voltage (V) Min 0.00 0.00 0.10 2.80 0.20 5.60 0.30 8.40 0.40 11.20 0.50 ...
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Table 13: Target Output Drive Characteristics (Three-Quarter Strength) Notes 1–3 apply to all values. Characteristics are specified under best and worst process variations/conditions. Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 11.76 0.70 13.72 0.80 15.68 0.85 16.66 0.90 ...
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Table 14: Target Output Drive Characteristics (One-Half Strength) Notes 1–2 apply to all values. Characteristics are specified under best and worst process variations/conditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 10.16 0.85 10.80 0.90 10.80 0.95 ...
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Functional Description Mobile SDRAMs are quad-bank DRAMs that operate at 1.8V and include a synchronous interface. All signals are registered on the positive edge of the clock signal, CLK. Read and write accesses to SDRAMs are burst oriented; accesses start ...
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Commands Table 15 provides a quick reference of available commands. A written description of each command follows the table. Three additional Truth Tables appear on pages 31–35; these tables provide current state/next state information. Table 15: Truth Table – Commands ...
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NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are ...
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Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal ...
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Figure 11: WRITE Command RAS# CAS# WE# Address A10 BA0, BA1 Notes enable auto precharge, DIS AP = disable auto precharge PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank ...
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Figure 12: PRECHARGE Command CLK CKE CS# RAS# CAS# WE# Address A10 BA0,1 BURST TERMINATE The BURST TERMINATE command is used to either truncate fixed-length or continuous page bursts. The most recently registered READ or WRITE command prior to the ...
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DEEP POWER-DOWN (DPD) The DEEP POWER-DOWN command causes the Mobile SDRAM to enter deep power- down mode. DPD is an operating mode used to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. ...
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Operations Truth Tables Table 16: Truth Table – Current State Bank n, Command to Bank n Notes 1–6; notes appear below this table Current State CS# RAS# CAS# Any Idle ...
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Read w/auto- precharge enabled: Write w/auto- precharge enabled: 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Accessing mode register: ...
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Table 17: Truth Table – Current State Bank n, Command to Bank m Notes 1–6; notes appear below this table Current State CS# RAS# CAS# Any Idle X X Row L L activating active, ...
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A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m ...
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Table 18: Truth Table – CKE Notes 1–4; notes appear below this table CKE CKE Current State n Power-down Self refresh Clock suspend Deep power-down L H Power-down Deep power-down Self refresh Clock suspend H L All ...
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When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode registers power unknown state, they should be ...
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Register Definition Mode Register There are two mode registers in the Mobile SDRAM component, the mode register and the extended mode register (EMR). The mode register is illustrated in Figure 14 on page 37. The mode register defines the specific ...
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Burst Length (BL) Read and write accesses to the SDRAM are burst oriented, with the BL being program- mable, as shown in Figure 14 on page 37. The BL determines the maximum number of column locations that can be accessed ...
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CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks ...
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Write Burst Mode When the BL programmed via M0–M2 applies to both READ and WRITE bursts; when the programmed BL applies to READ bursts, but write accesses are single- location (nonburst) accesses. Extended Mode ...
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Temperature-Compensated Self Refresh (TCSR) Micron Mobile SDRAM includes a temperature sensor that is implemented for auto- matic control of the self refresh oscillator on the device. Therefore recommended that the TCSR control bits in the EMR not be ...
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Figure 17: Example: Meeting CLK Command READs READ bursts are initiated with a READ command, as shown in Figure 10. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled ...
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Figure 18: Consecutive READ Bursts Command Address Command Address Notes: 1. Each READ command may be to any bank. DQM is LOW. PDF: 09005aef82ea3742/Source: 09005aef82ea3752 sdr_mobile_sdram_cmd_op_timing_dia_fr4.08__4.fm - Rev CLK READ NOP NOP Bank, Col ...
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Figure 19: Random READ Accesses Command Address Command Address Notes: 1. Each READ command may be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length ...
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The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 19 on page 44 shows the case where the clock frequency ...
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Figure 21: READ-to-WRITE with Extra Clock Cycle CLK DQM Command Address Notes The READ command may be to any bank, and the WRITE command may be to any bank. Figure 22: READ-to-PRECHARGE Command Address Command Address ...
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Continuous-page READ bursts may be truncated with a BURST TERMINATE command and fixed -length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles ...
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Figure 24: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable auto ...
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Figure 25: READ Continuous Page Burst CLK CKS t CKH CKE t CMS t CMH Command ACTIVE NOP READ t CMS DQM Address Row Column m ...
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Figure 26: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable auto ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 11 on page 28. The starting column and bank addresses are provided with the WRITE command and auto precharge is either enabled or disabled for that access. ...
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Figure 28: WRITE-to-WRITE Command Address Notes: 1. DQM is LOW. Each WRITE command may be to any bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be ...
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Figure 29: Random WRITE Cycles Command Address Notes: 1. Each WRITE command may be to any bank. DQM is LOW. Figure 30: WRITE-to-READ Command Address Notes: 1. The WRITE command may be to any bank, and the READ command may ...
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Figure 31: WRITE-to-PRECHARGE t WR@ DQM Command Address t WR@ DQM Command Address Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Fixed-length WRITE bursts can be truncated with the ...
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Figure 32: Terminating a WRITE Burst Command Address Notes: 1. DQM is LOW. Figure 33: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP WRITE ...
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Figure 34: WRITE – Continuous Page Burst CLK CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row Row A10 t ...
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Figure 35: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row Row A10 ...
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READ or WRITE burst, except in the continuous page burst mode, where auto precharge does not apply. In the specific case of write burst mode set to single location access with burst ...
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Figure 37: READ with Auto Precharge Interrupted by a WRITE CLK Command Page Bank n Active Internal States Bank m Address 1 DQM DQ Notes: 1. DQM is HIGH prevent D Figure 38: READ with Auto Precharge ...
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Figure 39: READ without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Row A10 ...
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Figure 40: Single READ with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row A10 Row t ...
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Figure 41: Single READ without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row Row ...
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WRITE with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank n ...
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Figure 44: WRITE with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP WRITE t CMS DQM Address Row Column ...
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Figure 45: WRITE without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP WRITE t CMS DQM Address Row Column ...
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Figure 46: Single WRITE with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP NOP DQM Address Row A10 ...
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Figure 47: Single WRITE without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row A10 ...
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Figure 48: Auto Refresh Mode T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH Command PRECHARGE NOP DQM Address All banks A10 Single bank BA0, BA1 Bank(s) High ...
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The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock ball) prior to CKE going back HIGH. After CKE ...
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CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no REFRESH operations are performed in this mode. ...
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Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which ...
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Figure 52: Clock Suspend During READ Burst Internal Command Address Notes: 1. For this example greater, and DQM is LOW. PDF: 09005aef82ea3742/Source: 09005aef82ea3752 sdr_mobile_sdram_cmd_op_timing_dia_fr4.08__4.fm - Rev CLK ...
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Figure 53: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH Command READ NOP t CMS t CMH DQM Address Column m ...
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Revision History: Device Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Revision History: Commands, Operations, and Timing Diagrams Revision History: Commands, Operations, and Timing Diagrams Update . . . . . . . . . . . . . . . . . . . . . . . . . ...