MT48H4M16LFB4-10 Micron Technology Inc, MT48H4M16LFB4-10 Datasheet - Page 42

IC SDRAM 64MBIT 100MHZ 54VFBGA

MT48H4M16LFB4-10

Manufacturer Part Number
MT48H4M16LFB4-10
Description
IC SDRAM 64MBIT 100MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48H4M16LFB4-10

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
64M (4M x 16)
Speed
100MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-VFBGA
Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
8/7ns
Maximum Clock Rate
104MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
50mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
MT48H4M16LFB4-10
Manufacturer:
MICRON
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4 000
Part Number:
MT48H4M16LFB4-10
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48H4M16LFB4-10 IT
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Micron Technology Inc
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Part Number:
MT48H4M16LFB4-10 IT TR
Manufacturer:
Micron Technology Inc
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Part Number:
MT48H4M16LFB4-10 TR
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Micron Technology Inc
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Part Number:
MT48H4M16LFB4-10:H
Manufacturer:
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Quantity:
4 000
NOTE:
NOTE:
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 = “Don’t Care.”
3. PRECHARGE command not allowed or
1. CAS latency indicated in parentheses.
SYMBOL
t
t
t
t
AC (3)
AC (2)
CK (3)
CK (2)
t
t
t
CKH
t
t
t
CKS
AH
CH
AS
CL
1
DQMU, DQML
COMMAND
A0-A9, A11
BA0, BA1
MIN MAX MIN MAX
2.5
9.6
2.5
1
3
3
8
1
CKE
CLK
A10
DQ
-8
t CMS
t CKS
t AS
t AS
t AS
100
100
ACTIVE
7
8
ROW
ROW
T0
BANK
Figure 38: Single READ – Without Auto Precharge
t CMH
t CKH
t AH
t AH
t AH
t RCD
t RAS
t RC
2.5
9.6
2.5
12
1
3
3
1
t CK
-10
T1
NOP
100
100
DISABLE AUTO PRECHARGE
7
8
t CMS
t CL
COLUMN m
BANK
T2
READ
t
UNITS
RAS would be violated.
t CMH
t CH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS Latency
2
T3
NOP
t LZ
3
t AC
42
T4
D
NOP
OUT
t OH
t HZ
3
m
SINGLE BANKS
PRECHARGE
ALL BANKS
BANK(S)
SYMBOL
T5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
t
HZ (3)
HZ (2)
t
t
t
CMH
t
CMS
RCD
RAS
t
t
t
OH
t RP
RC
RP
LZ
T6
NOP
MIN
2.5
48
80
19
19
1
1
3
ACTIVE
-8
ROW
BANK
120,000
T7
ROW
MAX
7
8
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
DON’T CARE
UNDEFINED
1
T8
NOP
MIN
2.5
50
66
20
20
1
1
3
64Mb: x16
-10
120,000
MAX
7
8
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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