MT48H4M16LFB4-10 Micron Technology Inc, MT48H4M16LFB4-10 Datasheet - Page 18

• Manufacturer Part Number: MT48H4M16LFB4-10
• Description: IC SDRAM 64MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H4M16LFB4-10

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTE:
NOTE:
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
Figure 13: READ to WRITE with Extra
COMMAND
ADDRESS
COMMAND
DQM
ADDRESS
CLK
DQ
Figure 12: READ to WRITE
A CAS latency of three is used for illustration.
The READ command may be to any bank,
and the WRITE command may be to any
bank. If a burst of one is used, then DQM is
not required.
A CAS latency of three is used for illustration.
The READ command may be to any bank,
and the WRITE command may be to any
bank.
DQM
CLK
DQ
BANK,
COL n
T0
READ
T0
BANK,
COL n
READ
T1
Clock Cycle
NOP
T1
NOP
T2
NOP
T2
NOP
T3
NOP
t HZ
D
T3
OUT
NOP
D
n
t HZ
OUT
t CK
n
T4
NOP
DON’T CARE
T4
BANK,
COL b
WRITE
D
IN
DON’T CARE
b
t
T5
BANK,
COL b
WRITE
DS
D
IN
b
t
DS
18
NOTE:
NOTE:
COMMAND
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
ADDRESS
Figure 15: Terminating a READ Burst
CLK
CLK
CLK
CLK
DQ
DQ
DQ
DQ
Figure 14: READ to PRECHARGE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK a,
BANK a,
T0
COL n
COL n
BANK,
T0
T0
COL n
READ
DQM is LOW.
T0
BANK,
DQM is LOW.
READ
READ
COL n
READ
CAS Latency = 2
CAS Latency = 2
CAS Latency = 3
CAS Latency = 3
T1
T1
T1
T1
NOP
NOP
NOP
NOP
T2
T2
T2
T2
NOP
NOP
NOP
NOP
D
D
OUT
n
OUT
n
T3
T3
TRANSITIONING DATA
T3
T3
NOP
NOP
NOP
NOP
MOBILE SDRAM
n + 1
D
D
n + 1
D
D
OUT
OUT
n
OUT
OUT
n
©2003 Micron Technology, Inc. All rights reserved.
TRANSITIONING DATA
PRECHARGE
PRECHARGE
TERMINATE
TERMINATE
(a or all)
(a or all)
T4
BANK
T4
BANK
T4
BURST
T4
BURST
X = 1 cycle
X = 1 cycle
D
n + 2
n + 1
D
n + 2
D
n + 1
D
OUT
OUT
OUT
OUT
64Mb: x16
X = 2 cycles
X = 2 cycles
T5
T5
T5
T5
NOP
NOP
NOP
NOP
n + 3
D
n + 2
D
D
n + 3
n + 2
D
OUT
OUT
OUT
OUT
t RP
t RP
T6
T6
T6
T6
NOP
NOP
NOP
NOP
D
n + 3
n + 3
D
OUT
OUT
DON’T CARE
DON’T CARE
BANK a,
BANK a,
ACTIVE
T7
T7
ACTIVE
T7
ROW
ROW
NOP