MT45W4MW16BCGB-701 WT TR Micron Technology Inc, MT45W4MW16BCGB-701 WT TR Datasheet - Page 39

• Manufacturer Part Number: MT45W4MW16BCGB-701 WT TR
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BCGB-701 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
Parameter
Address access time (fixed latency)
ADV# access time (fixed latency)
Burst to READ access time (variable latency)
CLK to output
delay
Address hold from ADV# HIGH (fixed latency)
Burst OE# LOW to output delay
CE# HIGH between subsequent burst or
mixed-mode operations
Maximum CE# pulse width
CE# LOW to WAIT valid
CLK period
Chip select access time (fixed latency)
CE# setup time to active CLK edge
Hold time from active CLK edge
Chip disable to DQ and WAIT High-Z output
CLK rise or fall time
CLK to WAIT
valid
Output hold from CLK
CLK HIGH or LOW time
Output disable to DQ High-Z output
Output enable to Low-Z output
Setup time to active CLK edge
Burst READ Cycle Timing Requirements
All tests are performed with outputs configured for default setting of one-half drive strength
(BCR[5:4] = 01b)
Variable LC = 4
Fixed LC = 8
All other LCs
Variable LC = 4
Fixed LC = 8
All other LCs
Notes:
1. Values are valid for
2. A refresh opportunity must be provided every
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The
4. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 37. The
-708.
either of the following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than
15ns.
High-Z timings measure a 100mV transition either from V
Low-Z timings measure a 100mV transition away from the High-Z (V
toward V
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
OH
or V
OL
Symbol
t
.
t
t
t
t
AADV
t
t
t
t
t
t
KHKL
t
ACLK
CBPH
KHTL
t
t
t
CEW
t
KOH
t
ABA
AVH
CEM
t
OHZ
BOE
t
CLK
t
t
OLZ
CLK (MIN) with no refresh collision: LC = 4 for -7013; LC = 3 for -701 and
CSP
t
AA
CO
HD
HZ
KP
SP
39
Min
(133 MHz)
7.5
2.5
1.5
2
5
1
2
3
3
2
–
–
–
–
–
–
–
–
–
–
–
–
–
-7013
Max
35.5
5.5
7.5
1.2
5.5
70
70
20
70
7
4
7
7
7
–
–
–
–
–
–
–
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Min
9.62
(104 MHz)
–
–
–
–
–
2
–
5
–
1
–
3
2
–
–
–
–
2
3
–
3
3
t
CEM. A refresh opportunity is satisfied by
-701
Max
35.9
1.6
7.5
70
70
20
70
7
7
–
–
4
–
–
–
7
7
7
–
–
7
–
–
OH
or V
Timing Requirements
Min
12.5
(80 MHz)
–
–
–
–
–
2
–
6
–
1
–
4
2
–
–
–
–
2
4
3
3
©2005 Micron Technology, Inc. All rights reserved.
OL
-708
toward V
CC
Max
46.5
7.5
1.8
70
70
20
70
Q/2) level either
9
9
–
–
4
–
–
–
7
9
9
–
–
7
–
–
CC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Q/2.
Notes
1
2
2
4
3
4