MT45W4MW16BCGB-7013 WT TR Micron Technology Inc, MT45W4MW16BCGB-7013 WT TR Datasheet
MT45W4MW16BCGB-7013 WT TR
Specifications of MT45W4MW16BCGB-7013 WT TR
Related parts for MT45W4MW16BCGB-7013 WT TR
MT45W4MW16BCGB-7013 WT TR Summary of contents
Page 1
... A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 J WAIT CLK ADV# RFU RFU RFU Top view (Ball down) Designator quency exceed the CellularRAM 1.5 Work- group specification. Part Number Example: MT45W4MW16BCGB-701LWT ©2005 Micron Technology, Inc. All rights reserved. Features None ...
Page 2
Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
List of Figures Figure 1: 54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
List of Tables Table 1: VFBGA Ball Descriptions ...
Page 5
... General Description Micron low-power, portable applications. The MT45W4MW16BCGB is a 64Mb DRAM core device, organized as 4 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans- parent self refresh mechanism ...
Page 6
Figure 2: Functional Block Diagram – 4 Meg x 16 A[21:0] CE# WE# OE# CLK Control ADV# logic CRE WAIT LB# UB# Note: Functional block diagrams illustrate simplified device operation. For detailed information, see ball descriptions in Table 1 on ...
Page 7
Table 1: VFBGA Ball Descriptions VFBGA Assignment Symbol Type E3, H6, G2, H1, A[21:0] Input D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 CLK Input J3 ADV# Input A6 ...
Page 8
Table 2: Bus Operations – Asynchronous Mode (BCR[15 Default) Mode Power Active Read Write Active Standby Standby No operation Idle Active Configuration register write Active Configuration register read DPD Deep power-down Notes: 1. CLK must be LOW during ...
Page 9
Table 3: Bus Operations – Burst Mode (BCR[15 Mode Power Active Asynchronous read Active Asynchronous write Standby Standby No operation Idle Active Initial burst read Initial burst Active write Burst Active continue Burst suspend Active Configuration Active register ...
Page 10
Part-Numbering Information Micron CellularRAM devices are available in several different configurations and densi- ties (see Figure 3). Figure 3: Part Number Chart Micron Technology Product Family 45 = PSRAM/CellularRAM memory Operating Core Voltage W ...
Page 11
... Functional Description In general, the MT45W4MW16BCGB device is a high-density alternative to SRAM and PSRAM products, popular in low-power, portable applications. The MT45W4MW16BCGB contains a 67,108,864-bit DRAM core, organized as 4,194,304 addresses by 16 bits. The device implements the same high-speed bus interface found on burst mode Flash products. ...
Page 12
Figure 5: READ Operation (ADV# LOW) CE# OE# WE# Address Data LB#/UB# Note: ADV must remain LOW for page mode operation. Figure 6: WRITE Operation (ADV# LOW) CE# OE# WE# Address Data LB#/UB# PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F ...
Page 13
Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is performed, and then adjacent addresses can be read quickly by simply changing the low-order address. ...
Page 14
Variable latency allows the CellularRAM to be configured for minimum latency at high clock frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles. Fixed latency outputs the first data ...
Page 15
Figure 9: Burst Mode WRITE (4-Word Burst) CLK A[21:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# Note: Nondefault BCR settings for burst mode WRITE (4-word burst): fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted ...
Page 16
Figure 10: Wired-OR WAIT Configuration Processor When a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until ...
Page 17
Figure 11: Refresh Collision During Variable-Latency READ Operation V IH CLK A[21:0] Valid address ADV ...
Page 18
Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion ...
Page 19
Access Using CRE The registers can be accessed either using a synchronous or an asynchronous operation when the control register enable (CRE) input is HIGH (see Figures 12 through 15). When CRE is LOW, a READ or WRITE operation will ...
Page 20
Figure 13: Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation CLK Latch control register value A[21:0] OPCODE (except A[19:18 A[19:18 CRE ADV CSP CE# ...
Page 21
Figure 14: Register READ, Asynchronous Mode Followed by READ ARRAY Operation A[21:0] (except A[19:18]) Select register 1 A[19:18] CRE t VPH ADV# CE# OE# WE# LB#/UB# DQ[15:0] Notes: 1. A[19:18] = 00b to read RCR, 10b to read BCR, and ...
Page 22
Figure 15: Register READ, Synchronous Mode Followed by READ ARRAY Operation CLK Latch control register value A[21:0] (except A[19:18 A[19:18 CRE t SP ADV CSP CE# OE# WE LB#/UB# t ...
Page 23
Software Access Software access of the registers uses a sequence of asynchronous READ and asynchro- nous WRITE operations. The contents of the configuration registers can be modified, and all registers can be read using the software sequence. The configuration registers ...
Page 24
Figure 17: Read Configuration Register Address CE# OE# WE# LB#/UB# Data PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory READ READ WRITE Address Address Address (MAX) (MAX) (MAX) XXXXh XXXXh ...
Page 25
Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 18 defines the control bits in the BCR. At power-up, the ...
Page 26
Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst length 16 words. The device can also ...
Page 27
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The reduced-strength options are intended for stacked chip (Flash + ...
Page 28
Figure 20: WAIT Configuration (BCR[ CLK WAIT DQ[15:0] Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 21 on page 28). Figure 21: WAIT Configuration During Burst Operation CLK WAIT WAIT DQ[15:0] ...
Page 29
Table 6: Variable Latency Configuration Codes (BCR [14 Latency BCR[13:11] Configuration Code 010 2 (3 clocks) 011 3 (4 clocks)—default 100 4 (5 clocks) Others Reserved Notes: 1. Latency is the number of clock cycles from the initialization ...
Page 30
Table 7: Fixed Latency Configuration Codes (BCR[14 Latency BCR[13:11] Configuration Code 010 2 (3 clocks) 011 3 (4 clocks)—default 100 4 (5 clocks) 101 5 (6 clocks) 110 6 (7 clocks) 000 8 (9 clocks) Others Reserved Figure ...
Page 31
Refresh Configuration Register The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure ...
Page 32
Table 8: 64Mb Address Patterns for PAR (RCR[ RCR[2] RCR[1] RCR[ Deep Power-Down (RCR[4]) ...
Page 33
Device Identification Register The DIDR provides information on the device manufacturer, the CellularRAM genera- tion, and the specific device configuration. Table 9 describes the bit fields in the DIDR. The DIDR is accessed with CRE HIGH and A[19:18] = 01b ...
Page 34
Electrical Characteristics Table 10: Absolute Maximum Ratings Parameter Voltage to any ball except Voltage on V supply relative Voltage supply relative Storage temperature (plastic) Operating temperature ...
Page 35
Table 11: Electrical Characteristics Wireless temperature (–30ºC < T Description Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current Notes Input signals ...
Page 36
Table 13: Partial-Array Refresh Specifications and Conditions Description Conditions Partial-array 0V refresh standby CE current Note: I PAR changes to the PAR array partition or when entering standby mode. ...
Page 37
Table 15: Capacitance Description Input capacitance Input/output capacitance (DQ) Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. Figure 26: AC Input/Output Reference Waveform Input V SS Notes test ...
Page 38
Timing Requirements Table 16: Asynchronous READ Cycle Timing Requirements All tests are performed with outputs configured for default setting of one-half drive strength (BCR[5:4] = 01b). Parameter Address access time ADV# access time Page access time Address hold from ADV# ...
Page 39
Table 17: Burst READ Cycle Timing Requirements All tests are performed with outputs configured for default setting of one-half drive strength (BCR[5:4] = 01b) Parameter Address access time (fixed latency) ADV# access time (fixed latency) Burst to READ access time ...
Page 40
Table 18: Asynchronous WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time Address hold from ADV# going HIGH Address setup to ADV# going HIGH Address valid to end of WRITE LB#/UB# select to end of WRITE CE# LOW ...
Page 41
Table 19: Burst WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time Address hold from ADV# HIGH (fixed latency) CE# HIGH between subsequent burst or mixed- mode operations Maximum CE# pulse width CE# LOW to WAIT valid Clock ...
Page 42
Timing Diagrams Figure 28: Initialization Period Vcc, VccQ = 1.7V Figure 29: DPD Entry and Exit Timing CE# Write DPD enabled RCR[ Table 20: Initialization Timing Parameters Parameter Time from DPD entry to DPD exit CE# LOW time ...
Page 43
Figure 30: Asynchronous READ A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address ...
Page 44
Figure 31: Asynchronous READ Using ADV# A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory V IH Valid address ...
Page 45
Figure 32: Page Mode READ A[21:4] A[3:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address V IL ...
Page 46
Figure 33: Single-Access Burst READ Operation – Variable Latency CLK A[21:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] Note: Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. ...
Page 47
Figure 34: 4-Word Burst READ Operation – Variable Latency V IH CLK A[21:0] Valid address ADV CSP V IH CE# V ...
Page 48
Figure 35: Single-Access Burst READ Operation – Fixed Latency V IH CLK A[21:0] Valid address ADV CSP OE# ...
Page 49
Figure 36: 4-Word Burst READ Operation – Fixed Latency V IH CLK A[21:0] Valid address AVH ADV CSP V IH CE# V ...
Page 50
Figure 37: READ Burst Suspend V IH CLK A[21:0] Valid address ADV CSP OE# ...
Page 51
Figure 38: Burst READ at End-of-Row (Wrap Off CLK CLK V IH A[21: ADV LB#/ ...
Page 52
Figure 39: CE#-Controlled Asynchronous WRITE A[21:0] ADV# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address V IL ...
Page 53
Figure 40: LB#/UB#-Controlled Asynchronous WRITE A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address V ...
Page 54
Figure 41: WE#-Controlled Asynchronous WRITE A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory V IH Valid address ...
Page 55
Figure 42: WE#-Controlled Asynchronous WRITE Using ADV# A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory V IH Valid address V ...
Page 56
Figure 43: Burst WRITE Operation – Variable Latency Mode V IH CLK A[21:0] Valid address ADV ...
Page 57
Figure 44: Burst WRITE Operation – Fixed Latency Mode V IH CLK A[21:0] Valid address ADV ...
Page 58
Figure 45: Burst WRITE at End of Row (Wrap Off CLK CLK V IH A[21: ADV LB#/UB CE WE# ...
Page 59
Figure 46: Burst WRITE Followed by Burst READ t CLK V IH CLK A[21:0] Valid address ADV LB#/UB ...
Page 60
Figure 47: Burst READ Interrupted by Burst READ or WRITE V IH CLK Valid A[21:0] address ADV CSP V IH CE# ...
Page 61
Figure 48: Burst WRITE Interrupted by Burst WRITE or READ – Variable Latency Mode V IH CLK A[21:0] Valid V address ADV ...
Page 62
Figure 49: Burst WRITE Interrupted by Burst WRITE or READ – Fixed Latency Mode V IH CLK A[21:0] Valid V address IL t AVH ADV ...
Page 63
Figure 50: Asynchronous WRITE Followed by Burst READ V IH CLK A[21:0] Valid address Valid address AVS t AVH ADV VPH t ...
Page 64
Figure 51: Asynchronous WRITE (ADV# LOW) Followed by Burst READ V IH CLK A[21:0] Valid address Valid address ADV LB#/UB ...
Page 65
Figure 52: Burst READ Followed by Asynchronous WRITE (WE#-Controlled CLK A[21:0] Valid address ADV CSP V IH CE# V ...
Page 66
Figure 53: Burst READ Followed by Asynchronous WRITE Using ADV CLK A[21:0] Valid address ADV CSP V IH CE# ...
Page 67
Figure 54: Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW V IH A[21:0] Valid address ADV LB#/ ...
Page 68
Figure 55: Asynchronous WRITE Followed by Asynchronous READ V IH A[21:0] Valid address AVS VPH V IH ADV CVS V IH LB#/UB CE ...
Page 69
... All dimensions are in millimeters; MAX/MIN or typical (TYP) where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W4MW16BCGB uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc ...