MT45W4MW16BCGB-701 WT TR Micron Technology Inc, MT45W4MW16BCGB-701 WT TR Datasheet - Page 16

• Manufacturer Part Number: MT45W4MW16BCGB-701 WT TR
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BCGB-701 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10:
LB#/UB# Operation
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
Wired-OR WAIT Configuration
When a READ or WRITE operation has been initiated, WAIT goes active to indicate that
the CellularRAM device requires additional time before data can be transferred. For
READ operations, WAIT will remain active until valid data is output from the device. For
WRITE operations, WAIT will indicate to the memory controller when data will be
accepted into the CellularRAM device. When WAIT transitions to an inactive state, the
data burst will progress on successive clock edges.
During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE#
HIGH during this initial latency may cause data corruption.
When variable initial access latency is used (BCR[14] = 0), the WAIT output performs an
arbitration role for READ operations launched while an on-chip refresh is in progress. If
a collision occurs, WAIT is asserted for additional clock cycles until the refresh has
completed (see Figure 11 on page 17). When the refresh operation has completed, the
READ operation will continue normally.
WAIT will be asserted but should be ignored during asynchronous READ, WRITE, and
PROGRAM operations.
By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst
mode without monitoring the WAIT signal. However, WAIT can still be used to deter-
mine when valid data is available at the start of the burst and at the end of a row. If WAIT
is not monitored, the controller must stop burst accesses at row boundaries on its own.
The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE
operations, any disabled bytes will not be transferred to the RAM array, and the internal
value will remain unchanged. During an asynchronous WRITE cycle, the data to be
written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
LB#/UB# must be LOW during READ cycles.
When both LB# and UB# are disabled (HIGH) during an operation, the device will
disable the data bus from receiving or transmitting data. Although the device will seem
to be deselected, it remains in an active mode as long as CE# remains LOW.
Processor
READY
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
WAIT
device
Other
CellularRAM
WAIT
16
WAIT
device
Other
Micron Technology, Inc., reserves the right to change products or specifications without notice.
External
pull-up/
pull-down
resistor
Bus Operating Modes
©2005 Micron Technology, Inc. All rights reserved.