IDT7130SA100J IDT, Integrated Device Technology Inc, IDT7130SA100J Datasheet
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IDT7130SA100J
Specifications of IDT7130SA100J
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IDT7130SA100J Summary of contents
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... Both devices provide two independent ports with sepa- rate control, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled permits the on chip circuitry of each port to enter a very low standby power mode. ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS PIN CONFIGURATIONS (1, BUSY INT ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial (2) V Terminal Voltage –0.5 to +7.0 TERM with Respect to GND T Operating 0 to +70 A Temperature T Temperature –55 ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Test Conditions CE I Dynamic Operating CC L Current (Both Ports Outputs open, Active) f ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS DATA RETENTION WAVEFORM TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 5V DATA OUT 775 ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Read Cycle t Read Cycle Time RC t Address Access Time AA t Chip Enable ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE DATA OUT I CC CURRENT I SS NOTES: 1. Timing depends on which signal is asserted last, 2. Timing ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/ ADDRESS (4) DATA OUT DATA IN TIMING WAVEFORM OF WRITE CYCLE NO. 2, ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Busy Timing (For Master lDT7130 Only) BUSY t Access Time from Address BAA BUSY t ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF WRITE WITH W R/ 'A' BUSY ' 'B' NOTES must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Interrupt Timing t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set ...
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... Port Disabled and in Power- Down Mode Mode DATA Data on Port Written Into Memory DATA Data in Memory Output on Port OUT High Impedance Outputs NOTES – – 10L 0R 10R BUSY data is not written. BUSY data may not be valid, see 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE ...
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... R = IL, INT the right port interrupt flag ( ) is asserted when the left port R writes to memory location 3FF (HEX) and to clear the interrupt INT flag ( ), the right port must access the memory location R 3FF. The message (8 bits) at 3FE or 3FF is user-defined, since addressable SRAM location. If the interrupt ...
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IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS ORDERING INFORMATION IDT XXXX A 999 Device Type Power Speed Package A A Process/ Temperature Range Commercial ( +70 C) Blank Military (– +125 ...