M25PE20-VMN6TP NUMONYX, M25PE20-VMN6TP Datasheet - Page 44

IC FLASH 2MBIT 75MHZ 8SOIC

M25PE20-VMN6TP

Manufacturer Part Number
M25PE20-VMN6TP
Description
IC FLASH 2MBIT 75MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet

Specifications of M25PE20-VMN6TP

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
2M (256K x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Cell Type
NOR
Density
2Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC N
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
256K
Supply Current
8mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25PE20-VMN6TPTR

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Instructions
6.17
44/64
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode.
The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S)
Low, followed by the instruction code on Serial Data input (D). Chip Select (S) must be
driven Low for the entire duration of the sequence.
The instruction sequence is shown in
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, t
Standby Power mode. Chip Select (S) must remain High at least until this period is over. The
device waits to be selected, so that it can receive, decode and execute instructions.
Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 24. Release from Deep Power-down (RDP) instruction sequence
S
C
D
Q
High Impedance
0
1
2
Instruction
3
4
5
6
Figure
7
24.
Deep Power-down mode
t
RDP
RDP
, the device is put in
Standby Power mode
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AI06807

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