IS43R32800B-5BL ISSI, Integrated Silicon Solution Inc, IS43R32800B-5BL Datasheet - Page 19

• Manufacturer Part Number: IS43R32800B-5BL
• Description: IC DDR SDRAM 256MBIT 144BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32800B-5BL

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: Mini BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 400mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure “MODE REGISTER
DEFINITION”. The Mode Register is programmed via the MODE REGISTER SET (MRS) command (with BA0 = 0 and
BA1 = 0) and will retain stored information until it is programmed again or the device loses power.
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify
the CAS latency, and A7-A11 specify the operating mode.
The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the
specified time before initiating any subsequent operation. After tMRD from a MRS command the DDR SDRAM is ready for
a new command. Violating either of these requirements will result in unspecified operation.
IS43R32800B
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08
BA 1 B A0 A11 A 10 A9
0
DL L R eset
0
0
Latency
Mode
0
0
1
0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
DR
CL
A8
A7
0
Y ES
NO
/CAS La tency
A6
MODE REGISTER DEFINITION
LT MO DE
2.5
R
R
R
R
R
2
3
A5
A4
A3
BT
A2
Burst Type
A1
BL
Le ngth
Burst
A0
R: Reserved for Future Use
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BL
A11-A0
0
1
CL K
/CLK
/CS
/RAS
/CAS
/WE
BA 0
BA 1
BT =0
Interleaved
R
R
R
R
R
Sequential
2
4
8
V
BT =1
R
R
R
R
R
2
4
8
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