IS43R32800B-5BL ISSI, Integrated Silicon Solution Inc, IS43R32800B-5BL Datasheet - Page 18

• Manufacturer Part Number: IS43R32800B-5BL
• Description: IC DDR SDRAM 256MBIT 144BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32800B-5BL

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: Mini BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 400mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FUNCTIONAL DESCRIPTION
The IS43R32800B is a 256Mb DDR SDRAM internally configured as a quad--bank DRAM. These 256Mb device contains
4 banks x 2,097,152 x32 bits. The DDR SDRAM uses a double--data--rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM consists of a single 2n-bit wide,
one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data
transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the
row). The address bits registered coincident with the READ or WRITE command are used to select the starting column
location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition, command descriptions and device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner.
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a DDR SDRAM from damaged
or multi functioning.
After these sequence, the DDR SDRAM is idle state and ready for normal operation.
IS43R32800B
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1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS for the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200cycles
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08