IS43R32800B-5BL ISSI, Integrated Silicon Solution Inc, IS43R32800B-5BL Datasheet
IS43R32800B-5BL
Specifications of IS43R32800B-5BL
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IS43R32800B-5BL Summary of contents
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... All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The IS43R32800B achieves very high speed clock rate up to 200 MHz packaged in 144-ball FBGA. KEY TIMING PARAMETERS Parameter ...
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... IS43R32800B FUNCTIONAL BLOCK DIAGRAM DLL Memory Array Mode Re gister Addres s B uffer A0 I/O Buffer Memory Memory Array Array Control C ircu itry Cl ock B uffer BA 0,1 CLK /CLK CKE Integrated Silicon Solution, Inc. — www.issi.com DQS0 - uffer Memory Array Control Signal B uffer /CS /RAS /CAS ...
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... IS43R32800B PIN CONFIGURATION Package Code: B 144-ball FBGA (Top View) (12.00mm x 12.00mm Body, 0.8mm Ball Pitch DQS0 DM0 VSSQ VDDQ NC VDDQ VSSQ VSSQ VDDQ VD D VSS VDDQ VSSQ VDDQ VSSQ G DQS2 DM2 NC VSSQ VDDQ VSSQ VDDQ VSSQ K /CAS / VSS / PIN DESCRIPTIONS CLK, /CLK ...
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... IS43R32800B PIN FUNCTIONS SYMBOL TYPE CL K, /CLK Input nput /CS I nput /RAS , /CAS, /WE I nput A0-1 1 Input BA 0,1 Input Input / Output DQ0-31 DQS0- 3 Input / Output DM0- 3 Input Power Supp Vss Power Supp ly DDQ Q Vref Input 4 DESCRIPTION Cl ock nd/CLK are differential clock inputs address and control input signals are sampled on the crossing of the positive edge negative edgeof /CLK ...
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... IS43R32800B FUNCTIONAL DESCRIPTION ISSI's 256-Mbit DDR SDRAM precharge , and auto / self refresh. E ach command is defined by control signals of /RA S, /CAS and /WE at CLK rising edge addition to 3 signals, / and A8 are usedas chip select, refresh option, and prechargeoption, respect ively. To know the detailed definition of commands, please see the command truth table ...
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... IS43R32800B COMMAND TRUTH TABLE COMMAND MNEMONIC DESEL Deselect NOP No Operation Row Address Entry & ACT Bank Activate PRE Single Bank Precharge PREA PrechargeAll Banks Column Address Entry WRITE & Write Column Addres s Entry & Write with WRITEA Auto-Precharge Column Address E ntry READ & ...
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... IS43R32800B FUNCTIONAL TRUTH TABLE Current State /CS /RAS /CAS /WE Address IDLE ROW AD(Au to- Precharge Disabled Integrated Silicon Solution, Inc. — www.issi.com Rev. 00D 03/19/08 C ommand Action TERM ILLE GAL WRITE ILLEGAL Bank Active, L atch PRE / PRE uto-Refresh Op-C ode, Mode ode Register Set ...
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... IS43R32800B FUNCTIONAL TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Addres Auto- Precharge Disabled READ with Auto-Precharge WRITE with Auto-Precharge Command Action X DES (Continue Burst to END) X NOP NO P (Continue Burst to END) BA TERM IL LE GAL Terminate Burst, L atchCA , B egin READ / READA Read, Determine Auto-Precharge ...
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... IS43R32800B FUNCTIONAL TRUTH TABLE (continued) Current State /CS /RAS /CAS /W E Address HARGI ROW ACTI VATING WRITER COVERING Integrated Silicon Solution, Inc. — www.issi.com Rev. 00D 03/19/08 Command X DES EL X NOP BA TERM READ / WRITE PRE / PRE A X REF A I LLEGAL Op-C ode, M ode- ...
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... IS43R32800B FUNCTIONAL TRUTH TABLE (continued) Current State / CS /RAS /C AS /WE Address REFRESHING MODE REGISTER SETTING ABBREVIATIONS : H=Hi gh Level, L= Low L evel, X =Don't Care BA =Bank A ddress, R A=Row A ddress, CA =Column Address, NOP =No Operation NO TES : entries assume that CK E was Hi gh during the preceding clock cycle and the current clock cycle. ...
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... IS43R32800B CKE TRUTH TABLE Curren t State CKE n-1 CKE n / SELF - REFR ESHI POWER DOWN ALL BANKS IDLE ANY STATE other than listed above ABBR EVIATI ONS : H=Hi gh Level, L= Low L evel, X =Don't Care NO TES : 1. CKE transition will re-enable CLK and other inputs asynchronously. ...
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... IS43R32800B STATE DIAGRAM POWE POWER PREA ON MODE REGISTER REFS MR S REFSX MR S REFA ID LE CKEL CKEH Active AC T Power Down CKEL CKEH Integrated Silicon Solution, Inc. — www.issi.com POWER DOW ADA Automatic Seque nce Command Sequence Rev. 00D 03/19/08 ...
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... IS43R32800B ABSOLUTE MAXIMUM RATINGS Sym bol Parameter V Supply V oltage DD V Supply Voltage for Output DDQ VI Input V oltage VO Output Voltage IO Output Current Pd Power Dissipation T opr Op erating Temperature Ts tg Storage Temperature DC OPERATING CONDITIONS Pa rame ter Supply Voltage Supply Voltage for Output High-Le vel I nput Voltage ...
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... IS43R32800B AVERAGE SUPPLY CURRENT FROM 2.5V + 0.2V ssQ = 0V , Output Open, unless otherwise noted DD DDQ Symbol ter/ T estCondition s OPER URRENT : One Bank; A ctive-Read-Precharge ;Burst = 2; IDD1 tRC = OUT = 0mA; A ddress andcontrol inputs chang ing o nce per clock cycle PR ECHA ER- DOW NDB Y C URRENT : A ll banks idle; ...
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... IS43R32800B AC TIMING REQUIREMENTS Sy mbol AC Ch arac terist aram eter tAC D Q Output access time from CLK //CL K tDQS CK DQS O utput access time from CLK //CL K tCH C LK Highlevel width tCL C LK Low level width tCK ycle time tDS I nput Setup time (DQ ,DM) ...
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... IS43R32800B AC TIMING REQUIREMENTS (Continued mbol AC Ch aract e risticsPa rame ter tRAS Row Active time tRC R ow Cycle time(operation) tRFC Auto Ref. to Active/Auto Ref. command period tRCD Row to Column Delay tRP R ow Precharge time tRRD Act to Act Delay time tWR W rite Recovery time ...
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... IS43R32800B Notes voltages referenced to Vss. 2. Tests for AC timing, I DD, and electrical, AC and DC characteristics, may be conducted at nominal reference/suppl y voltagelevels, but the related specifications and device operation are guaranteed for the full voltagerange specified timing and IDD tests may use swing 1. the test environment, but inputtiming is still referenced (or to the crossing point for CK //CK), and parameter specifications are guaranteedfor the specified AC input levels under normal use conditions ...
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... IS43R32800B FUNCTIONAL DESCRIPTION The IS43R32800B is a 256Mb DDR SDRAM internally configured as a quad--bank DRAM. These 256Mb device contains 4 banks x 2,097,152 x32 bits. The DDR SDRAM uses a double--data--rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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... IS43R32800B REGISTER DEFINITION MODE REGISTER The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure “MODE REGISTER DEFINITION”. The Mode Register is programmed via the MODE REGISTER SET (MRS) command (with BA0 = 0 and BA1 = 0) and will retain stored information until it is programmed again or the device loses power ...
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... IS43R32800B Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure “CAS LATENCY”. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths locations are available for both the sequential and the interleaved burst types ...
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... IS43R32800B CAS LATENCY /CLK CL K Read Command Address Y DQS /CAS tency BURST DEFINITION Initial A ddress Integrated Silicon Solution, Inc. — www.issi.com Rev. 00D 03/19/ Burst Length Column Addressing Sequen tial ite Burst Length Interleaved ...
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... IS43R32800B EXTENDED MODE REGISTER The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output drive strength selection (optional). These functions are controlled via the bits shown in Figure EXTENDED MODE REGISTER. The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power ...
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... IS43R32800B Read Operation /CLK & Add Write tion / tDQSS=max. /CLK CL K tDQS S tWPR tWPR E DQ Write tion / tDQSS=min. /CLK CL K tDQS tWPR ES tWPR E DQ Integrated Silicon Solution, Inc. — www.issi.com Rev. 00D 03/19/08 tCK tCH tDQS CK tQH tAC tDSS tDQS L tDQS H ...
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... IS43R32800B OPERATIONAL DESCRIPTION BANK ACTIVATE The DDR SDRAM has four independent banks. E ach bank is activated by the ACT command with the bank addresses (BA 0,1). A row is indicated by the row address A0-11. The minimum activation interval betweenone bank and the other bank is tRRD . PRECHARG E The PRE command deactivates the bank indicated by BA 0,1 ...
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... IS43R32800B READ Af ter tRCD from the bank activation, a REA D command can be issued. 1st Output data is available after the /CAS La tency from the followed by (BL-1 ) consecutive data when the Burst Le ngth start address is specified by A0 -7,9, and the address seque nce of burst data is defined by the Burst Ty pe ...
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... IS43R32800B READ with Auto-Prech arge(BL=8, CL=2,2.5,3. /CLK CL K Command AC T tRCD Xa A0-7 ,9- 0,1 00 DQS DQS CL =2.5 DQ DQS CL =3 tRP tRP Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa0 Qa1 Qa2 Qa3 Qa4 Qa0 Qa1 Qa2 Qa3 Internal Precharge Start Timing Integrated Silicon Solution, Inc. — www.issi.com ...
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... IS43R32800B WRITE Af ter tRCD from the bank activation, a WRI TE command can be issued. 1st input data is set from the WRI TE command with data strobe input, following ( data are written into RA M, when the Burst Length start address is specified by A0 -7,9, and the address seque nce of burst data is defined by the Burst Type ...
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... IS43R32800B WRITE w ith A uto-Prechar /CLK CL K Command tRC A0-7 ,9- 0,1 DQS Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Integrated Silicon Solution, Inc. — www.issi.com tDAL Rev. 00D 03/19/08 ...
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... IS43R32800B BURST INTERRUPTION Read I nterru pted by Read Burst read operation can be interrupted by new read of any bank. R andom column access is allowed interval is minimum 1CL K. /CLK CL K Command A0-7 ,9- 0,1 DQS DQ R ead I nterru pted by prechar ge Burst read operation can be interrupted by precharge of the same bank PRE interval is minimum ...
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... IS43R32800B /CLK CL K Command DQS DQ Command DQS CL Command DQS DQ /CLK CL K Command DQS DQ Command DQS CL Command DQS DQ 30 Read Int err upted by Prechar Read Int err upted by Prechar Integrated Silicon Solution, Inc. — www.issi.com Rev. 00D 03/19/08 ...
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... IS43R32800B Read I nterru pted Stop Burst read operation can be interrupted by a burst stop command(TE RM interval is minimum command to output disable latency is equivalent to the / atency result interval determines valid data length to be output. The figure below shows examples of B L=8. /CLK CL K Command ...
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... IS43R32800B /CLK CL K Command DQS DQ Command DQS CL Command DQS DQ R ead I nterru pted by Wr ite with /CLK CL K Command DQS CL=2 .0 Command DQS CL=2 .5 Command DQS CL Read Int err upted by TER = Read Int err upted by TER = TER TER TER Integrated Silicon Solution, Inc. — www.issi.com ...
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... IS43R32800B W rite interr uptedby Write Burst write operation can be interrupted by write of any bank. R andom column access is allowed. WRIT E to WRI TE interval is minimum /CLK CL K Command A0-7 ,9- 0 DQS DQ Dai1 Dai0 Wri te interr upted by Read Burst write operation can be interrupted by read of the same or the other bank. Ra ndom column access is allowed. I nternal command interval(tWT R) is minimum The inputdata the interrupting REA D cycle is " ...
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... IS43R32800B interrupted by Pr echarge Burst write operation can be interrupted by precharge of the same or all bank. Ra ndom column access is allowed. tWR is referenced from the first positive dgeafter the last data input. Wr ite Interr upted by Prechar ge (B L=8, CL=2 .5) /CLK Command A0-7 ,9- 0 Dai0 ...
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... IS43R32800B I nitial ize and Mode Registersets /CLK Command NOP PR E A0-7 ,9- 0,1 DQS DQ Ex tendedMode Register Set AUTO R EFRESH Single cycle of auto-refresh is initiated with a REF A( /CS=/R AS =/CA S=L, /WE=CK E=H) command. The refresh address is generated internally. 4096 RE FA cycles within 64ms refresh 256Mbits memory cells ...
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... IS43R32800B S ELF REFRESH Self -refresh mode is entered by issuing a REF S command (/CS=/RA S=/CAS =L ,/WE =H Once the self-refresh is initiated maintained as long kept low. During the self- refresh mode asynchronous and the only enable input , all other inputs including disabled and ignored, so that power consumption dueto synchronous inputs is saved exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting longer than tX SNR/ tXSRD ...
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... IS43R32800B P ower DOWN The purpo uspend is power down synchronous input except during the self- refresh mode ommand at cycle is ignored. F rom CKE =H to normal function recovery time is NOT required in the condition of the stable CLK operation during the power down mode. /CLK Command ...
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... IS43R32800B-6BL 133 MHz 7.5 IS43R32800B-75B 133 MHz 7.5 IS43R32800B-75BL Industrial Range: - +85 o Frequency Speed Order Part No. (ns) 200 MHz 5 IS43R32800B-5BI 200 MHz 5 IS43R32800B-5BLI 166 MHz 6 IS43R32800B-6BI 166 MHz 6 IS43R32800B-6BLI 133 MHz 7.5 IS43R32800B-75BI 133 MHz 7.5 IS43R32800B-75BLI Organization Package 8Mx32 ...
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... IS43R32800B Mini Ball Grid Array Package Code: B (144-Ball SEATING PLANE mBGA - 12mm x 12mm MILLIMETERS Sym. Min. Typ. Max. N0. Leads 144 A 1.17 1.25 1.40 A1 0.32 0.35 0.38 D 11.95 12.00 12.05 D1 — 8.80 — E 11.95 12.00 12.05 E1 — 8.80 — e — 0.80 — ...