IS43R16160B-5TL-TR ISSI, Integrated Silicon Solution Inc, IS43R16160B-5TL-TR Datasheet - Page 19

• Manufacturer Part Number: IS43R16160B-5TL-TR
• Description: IC DDR SDRAM 256MBIT 66TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS43R16160B-5TL-TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOPII
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 700ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43R83200B
IS43R16160B, IC43R16160B
Integrated Silicon Solution, Inc.
Rev. B
10/31/08
AVERAGE SUPPLY CURRENT from Vdd
IDD4W
Symbol
IDD2N
IDD3P
IDD3N
IDD4R
IDD2P
IDD1
IDD5 AUTO REFRESH CURRENT: t RC = t RFC (MIN)
IDD6 SELF REFRESH CURRENT: CKE < 0.2V
(
OPERATING CURRENT: One Bank; Active-Read-Precharge;Burst = 2; t
RC = t RC MIN; t CK = t CK MIN; IOUT= 0mA; Address and control
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE <VIL (MAX); t CK = t CK MIN
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cycle
ACTIVE POWER DOWN STANDBY CURRENT: One bank active;power
down mode;CKE
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN);
One bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN;
DQ,DM and DQS inputs changing twice per clock cycle; address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst =2; Read ; Continuous burst;All banks
active; Address and control inputs changing once per clock cycle;t CK = t
CK MIN; IOUT = 0 mA
OPERATING CURRENT: Burst =2; Write ; Continuous burst;All banks
active; Address and control inputs changing once per clock cycle;t CK = t
CK MIN; DQ and DQS inputs changing twice per clock cycle
o
C (Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
VIL(MAX);t CK = t CK MIN
Parameter/Test Conditions
185
30
50
95
290
290
170
60
-5
5
Limits(Max.)
55
45
90
250
250
25
160
165
-6
5
150
75
210
210
150
-75
50
20
40
5
Unit
mA
Notes
19