LFE3-95EA-V-EVN Lattice, LFE3-95EA-V-EVN Datasheet - Page 8

• Manufacturer Part Number: LFE3-95EA-V-EVN
• Description: Programmable Logic IC Development Tools LatticeECP3-95EA Video Protocol Board
• Manufacturer: Lattice
• Type: FPGAr

Specifications of LFE3-95EA-V-EVN

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: LFE3-95E-7FN1156C
• Interface Type: DVI
• Operating Supply Voltage: 12 V
• Description/function: LatticeECP3 Video protocol board
• Factory Pack Quantity: 1

On-Board Flash Memory
One SPI (16-pin TSSOP 64M) Flash memory device (U32) is on board for non-volatile configuration memory stor-
age. The CFG [2:0] setting must be [000] for the LatticeECP3 to enable the SPI Flash mode.
Video Clock Management and SDI Cable Driver/Equalizer
Industry standard video clocks are generated and managed via Gennum chipsets. These chipsets are used to gen-
erate both transmit and receive reference clocks for LatticeECP3 SERDES. The GS4911 clock generator device
produces multiple video standard reference clocks from an on-board 27MHz crystal. The GS4915 clock cleaner is
used to reduce clock jitter to produce a clean clock for video signal quality using a high-performance VCO. The
Gennum clock devices are used to generate clocks for SD/HD/3G-SDI applications. Since the PLL in LatticeECP3
FPGAs is designed to support all the frequencies required by SD/HD/3G-SDI, the GS4911 clock generator is no
longer needed. The two GS4911 devices found on the Revision B board are included on the Revision C board but
not populated.
Two cable drivers and two cable equalizers are placed on-board for SD/HD/3G-SDI applications that require deliv-
ering video signal over 75 ohm coaxial cable.
The control and status pins of the Gennum chipsets and the cable drivers/equalizers are connected to the MachXO
I/O pins. By using the signals connected between the MachXO and LatticeECP3, the Gennum chipsets and cable
drivers/equalizers can be controlled from the design in the LatticeECP3. Figure 3 shows the block diagram of the
control/status buses of the connections between these devices. The MachXO pins connected to these devices are
shown in Tables 9 to 12.
Figure 3. Block Diagram of Gennum Chipsets and Cable Driver/Equalizer Controls
SDI Rx #1
SDI Rx #0
SDI Tx #1
SDI Tx #0
Equalizer
Equalizer
Cable
Driver
Cable
Cable
Driver
Cable
(U24)
(U21)
(U22)
(U25)
Generator
Generator
Rx Refclk
Tx Refclk
GS4911
GS4911
(U2)
(U3)
RX_GS4911_RESETn
TX_GS4911_RESETn
LatticeECP3 Video Protocol Board – Revision C
MachXO
8
Rx Refclk
Tx Refclk
GS4915
GS4915
Cleaner
Cleaner
(U6)
(U7)
12
LatticeECP3
User’s Guide