LFE3-95EA-V-EVN Lattice, LFE3-95EA-V-EVN Datasheet - Page 10

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LFE3-95EA-V-EVN

Manufacturer Part Number
LFE3-95EA-V-EVN
Description
Programmable Logic IC Development Tools LatticeECP3-95EA Video Protocol Board
Manufacturer
Lattice
Type
FPGAr
Datasheet

Specifications of LFE3-95EA-V-EVN

Rohs
yes
Product
Evaluation Boards
Tool Is For Evaluation Of
LFE3-95E-7FN1156C
Interface Type
DVI
Operating Supply Voltage
12 V
Description/function
LatticeECP3 Video protocol board
Factory Pack Quantity
1
Table 12. MachXO Pin Connections GS2974 Cable Equalizer Devices
Table 13. MachXO Pin Connections to LatticeECP3
The status pins of these devices can also be observed from LED indicators. Table 13 shows the these LEDs with
the associated signals.
Table 14. LED Indicators for Video Clocking and Cable Equalizer Status
SERDES
There are three SERDES quads available for the LatticeECP3-95. Each quad include four SERDES channels.
These 12 SERDES channels are used for implementing high-speed serial link interfaces. Figure 4 shows the how
these channels are used.
LED #
D4
D1
D3
D2
D5
D6
D9
D8
Signal Type
Control
Status
Orange
Green
Color
Red
Rx GS4911 REF LOST
Tx GS4911 REF LOST
Rx GS4911 LOCK LOST LED illuminates to indicate the GS4911 clock output is not genlocked to
Tx GS4911 LOCK LOST
Rx GS4915 LOCK
Tx GS4915 LOCK
SDI Rx #0 Carrier Detect LED illuminates to indicate that the equalizer has detected the presence
SDI Rx #1 Carrier Detect
Driver Pin Name
ECP3_XO_SIG0
ECP3_XO_SIG1
ECP3_XO_SIG2
ECP3_XO_SIG3
ECP3_XO_SIG4
ECP3_XO_SIG5
ECP3_XO_SIG6
ECP3_XO_SIG7
ECP3_XO_SIG8
ECP3_XO_SIG9
ECP3_XO_SIG10
ECP3_XO_SIG11
MCLADJ
BYPASS
MUTE
Net Name
/CD
Function
potentiometer VR3
LED illuminates to indicate that no reference signal is applied or the
FSYNC, VSYNC, HSYNC input reference signals do not meet the
min/max timing requirement.
the input reference signals.
LED illuminates to indicate that the GS4915 output clock is locked to the
input clock selected by IPSEL.
of a good input video signal.
U25 (for Rx #0)
Controlled by
MachXO Pin
LatticeECP3 Video Protocol Board – Revision C
B10
N3
C3
P3
P4
A9
A7
A6
A5
B4
A3
B3
A2
A1
B2
10
LatticeECP3 Pin
potentiometer VR2
U21 (for Rx #1)
Controlled by
AM31
AM32
AN31
AN32
AL31
AP31
AB33
AB34
Y31
Y32
Y33
Y34
Description
N8
P8
P9
Pull-low/high
User’s Guide
Low
Low

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