LFE3-95EA-V-EVN Lattice, LFE3-95EA-V-EVN Datasheet - Page 14

• Manufacturer Part Number: LFE3-95EA-V-EVN
• Description: Programmable Logic IC Development Tools LatticeECP3-95EA Video Protocol Board
• Manufacturer: Lattice
• Type: FPGAr

Specifications of LFE3-95EA-V-EVN

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: LFE3-95E-7FN1156C
• Interface Type: DVI
• Operating Supply Voltage: 12 V
• Description/function: LatticeECP3 Video protocol board
• Factory Pack Quantity: 1

Table 18. SERDES PCI Express Interconnections (Continued)
Quad C (Daughter Board Expansion)
All channels of Quad 2 are connected to a high-speed Molex Mezzanine connector for working with a 3.2 x 2.5”
daughter board. Users can design a daughter board for implementing anything that requires the SERDES quad,
such as the high-speed HDMI/DVI video interface.
Figure 7. Daughter Board Connection
Other than the four input/output Quad 2 SERDES channels and the differential reference clock pair, there are three
differential pairs of general purpose I/Os connected between the Mezzanine connector and the LatticeECP3
device. These signals can be used for the control or status signals of the daughter board. A 4-pin power connector
is used to provide power to the daughter board. Tables 19 and 20 show the pin connections of the Mezzanine and
the power connectors. Table 21 shows the pin connections between the LatticeECP3 and the daughter board con-
PCI Express
REFCLK+
REFCLK-
PERST#
PERp1
PERn1
PERp2
PERn2
PERp3
PERn3
PETp0
PETn0
PETp1
PETn1
PETp2
PETn2
PETp3
PETn3
Name
Hole for standoffs
to secure the
Daughter Board
Daughter Board
Control Connector
(J47)
Daughter Board
Power Connector
(J17)
Mezzanine
Connector
(J19)
PCI Express
Pin #
A21
A22
A25
A26
A29
A30
B14
B15
B19
B20
B23
B24
B27
B28
A13
A14
A11
D
D
P
P
R
T
x
x
PCSB_HDOUTP1
PCSB_HDOUTN1
PCSB_HDOUTP2
PCSB_HDOUTN2
PCSB_HDOUTP3
PCSB_HDOUTN3
PCSB_HDINP0
PCSB_HDINN0
PCSB_HDINP1
PCSB_HDINN1
PCSB_HDINP2
PCSB_HDINN2
PCSB_HDINP3
PCSB_HDINN3
PCSB_REFCLKP
PCSB_REFCLKN
PT109A
3.2" x 2.5"
LatticeECP3
Pin Name
MDR
LatticeECP3
Lattice
ECP3
LatticeECP3 Video Protocol Board – Revision C
AN16
AN15
AN14
AH15
AH16
Pin #
AP16
AP15
AP14
AK17
AK16
AK15
AK14
AL17
AL16
AL15
AL14
J21
14
MDR
Coupling
MDR
C372
C375
C376
C379
C382
C383
None
None
None
None
None
None
None
None
None
None
None
AC
Power
Receiver differential pair, Lane 1
Receiver differential pair, Lane 2
Receiver differential pair, Lane 3
Transmitter differential pair, Lane 0
Transmitter differential pair, Lane 1
Transmitter differential pair, Lane 2
Transmitter differential pair, Lane 3
Reference clock (differential pair)
Fundamental reset
MDR
PCI Express Pin Description
User’s Guide