LFE3-95EA-V-EVN Lattice, LFE3-95EA-V-EVN Datasheet - Page 12

• Manufacturer Part Number: LFE3-95EA-V-EVN
• Description: Programmable Logic IC Development Tools LatticeECP3-95EA Video Protocol Board
• Manufacturer: Lattice
• Type: FPGAr

Specifications of LFE3-95EA-V-EVN

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: LFE3-95E-7FN1156C
• Interface Type: DVI
• Operating Supply Voltage: 12 V
• Description/function: LatticeECP3 Video protocol board
• Factory Pack Quantity: 1

Quad A (3G-SDI and DisplayPort Video Interfaces)
Quad 0 is used for SDI and DisplayPort video protocols. Channel 0 and 1 of quad 0 are used for SD/HD/3G-SDI.
The SD/HD/3G-SDI video signal is a signal-ended video signal transmitting through 75-ohm coaxial cable connect-
ing through BNC connectors. Two cable drivers and two cable equalizers are placed on board for using longer
coaxial cable. Channels 2 and 3 are used for support Displayport up to two data lanes.
Table 16 shows the ECP3 connections for the SD/HD/3G-SDI video interface connectors.
Table 16. SD/HD/3G-SDI Connections (J1, J2, J5 and J6)
There are two instances of Gennum clocking circuitry on this board, one for Rx side and the other for Tx side. Since
the specification of the high-speed video output stream jitter is critical, it is important to have a clean reference
clock for the Tx side serializer. The reference clock of the SERDES channel can come from different a path, but the
clock coming in through the dedicated reference clock pins will have the lowest jitter.
The dedicated reference clock pins of quad 0 can be sourcing from the following clocks:
• Clock generated by the on-board Gennum clocking chipsets
• Clock generated by the Silicon Labs Si570
• External differential clock coming through the two SMA connectors
Other than generating from the Gennum chipsets, the transmit reference clock can also receive input clock from an
external clock source via a pair of SMA connectors, or from the on-board Silicon Labs Si570. To avoid PCB trace
stub and minimize the jitter of the Tx reference clock, two zero-ohm resistors are used for selecting the clock from
one of the three clock sources. Figure 5 shows how these two zero-ohm resistors are installed to select a differ-
ence clock source. See the schematic in Appendix A (Figure 16) for the detailed clock multiplexing circuitry.
Figure 5. Resistors for Quad 0 Reference Clock Selection
Figure 6 shows the block diagram of the DisplayPort circuitry on this board. Since only two channels in SERDES
Quad 0 are used, the DisplayPort video interface on this board can only support up to two lanes. Two instances of
3.3V voltage regulators are used for providing power to the off-board DisplayPort devices when necessary.
Connector
J5
J6
J2
J1
TP11
TP12
R48
R47
TP13
TP14
Description
SDI Rx #0
SDI Rx #1
SDI Tx #0
SDI Tx #1
Select clock from
Gennum chipsets
On-board Default
Cable Driver/Equalizer
Equalizer (U25)
Equalizer (U21)
Driver (U22)
Driver (U24)
LatticeECP3 Video Protocol Board – Revision C
12
Select clock from
SMA connectors
PCSA_HDOUT[P:N]0
PCSA_HDOUT[P:N]1
SERDES Pin Names
PCSA_HDIN[P:N]0
PCSA_HDIN[P:N]1
Silicon Labs Si570
Select clock from
LatticeECP3 Pin #
User’s Guide
AP21, AN21
AP20, AN20
AL21, AK21
AL20, AK20