AT25DF641-MWH-Y Atmel, AT25DF641-MWH-Y Datasheet - Page 9

• Manufacturer Part Number: AT25DF641-MWH-Y
• Description: IC FLASH 64MBIT 100MHZ 8VDFN
• Manufacturer: Atmel

Specifications of AT25DF641-MWH-Y

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VDFN
• Architecture: Sectored
• Interface Type: SPI Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 19 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 128
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 5ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VDFN
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.
6.1.
3680F–DFLASH–4/10
Read Commands
Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by
simply providing the clock signal once the initial starting address has been specified. The device incorporates an
internal address counter that automatically increments on every clock cycle.
Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each opcode depends
on the maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at
any clock frequency up to the maximum specified by f
read operations up to the maximum specified by f
possible and can be used at any clock frequency up to the maximum specified by f
opcode at clock frequencies above f
To perform the Read Array operation, the
03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be
clocked in to specify the starting address location of the first byte to read within the memory array. Following the
three address bytes, additional dummy bytes may need to be clocked into the device depending on which opcode
is used for the Read Array operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the
device after the three address bytes. If the 0Bh opcode is used, then a single dummy byte must be clocked in
after the address bytes.
After the three address bytes (and the dummy bytes or byte if using opcodes 1Bh or 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a
byte first. When the last byte (7FFFFFh) of the memory array has been read, the device will continue reading
back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of
the array to the beginning of the array.
Deasserting the
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-1.
SCK
CS
SO
SI
Read Array - 1Bh Opcode
CS
MS B
HIGH-IMPE DANCE
0
0
pin will terminate the read operation and put the SO pin into a high-impedance state. The
0
1
0
2
OPCODE
1
3
1
4
0
5
1
6
1
7
MS B
A
8
CLK
A
9
ADDR E S S BITS A23-A0
should be reserved to systems employing the RapidS protocol.
A
10 11
A
CS
A
12
A
pin must first be asserted and the appropriate opcode (1Bh, 0Bh, or
A
29 30
RDLF
A
A
31 32
CLK
. The 1Bh opcode allows the highest read performance
MS B
X
, and the 03h opcode can be used for lower frequency
X
33
DON'T CAR E
X
34
X
35
X
36
X
37 38
X
X
39
MS B
X
40
X
41
DON'T CAR E
X
42 43
Atmel AT25DF641
X
X
44
X
45
MAX
X
46
X
; however, use of the 1Bh
47 48
MS B
D
D
49
DATA BYTE 1
D
50 51
D
D
52
D
53
D
54
D
55 56
MS B
D
D
CS
9